Datasheet

FIFO Memory Access
65
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
6 FIFO Memory Access
The TSB12LV32 FIFO interfaces with the microcontroller, the CFR and the 1394 link layer controller (LLC).
The FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF), each
of 520 quadlets (2K bytes). The FIFO provides storage for transmit packets (ATF) and receive packets (GRF).
When an asynchronous packet is confirmed into the ATF, the transmitter of the LLC requests the 1394 bus
to send the asynchronous packet. When a received packet is confirmed into the GRF by the receiver of the
LLC without any errors, interrupt RXGRFPKT in the interrupt register at 0Ch is triggered so the microcontroller
interface can read the received data from the GRF. Access to all FIFO memories is fundamentally the same,
only the address written to changes. Figure 6−1 shows the FIFO-address access map.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ATF_First
ATF_Continue
ATF_Continue&Update
GRF Data
50h
54h
58h
5Ch
60h
64h
68h ATF_First_Update
ATF_Burst_Write
Reserved
Figure 6−1. TSB12LV32 Controller-FIFO-Access Address Map
6.1 General
The suffix _First in Figure 6−1 denotes an address that accesses the FIFO location where the first quadlet of
a packet should be written to transmit the packet. The first quadlet is held in the FIFO until a quadlet is written
to an Update address and the packet is transmitted. The suffix _Continue in Figure 6−1 denotes an address
that accesses the FIFO location where the second through n–1 quadlets of a packet should be written, where
n is the total number of quadlets in the packet. The second through n–1 quadlets are held in the FIFO until
a quadlet is written to an Update address and the packet is transmitted. The suffix _Continue & Update in
Figure 6−1 denotes an address that accesses the FIFO location where the last quadlet of a multiple (n) quadlet
packet should be written so that the packet is confirmed for transmission.
6.2 ATF Access
The ATF consists of a 520 quadlet RAM, a write buffer, and control logic. The ATF write buffer is a four-quadlet
buffer used to temporarily store asynchronous packet data from the microcontroller interface to facilitate burst
writes. Asynchronous packets can also be transmitted through the data-mover port, however the ATF always
has transmission priority and its data will be sent first.
The procedure for accessing the ATF for a quadlet write operation is accomplished in three successive steps.
To ensure that an ATF underflow condition does not occur, loading of the ATF in the following manner is highly
recommended.
First Quadlet of the Packet
Successive (N−1) Quadlets of the Packet
•
•
•
Last (N
th
) Quadlet of the Packet
Figure 6−2. Asynchronous Packet With N Quadlets (ATF Loading Operation)