Datasheet

Data-Mover Port Interface
63
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.5 Data-Mover Handshake Mode
In this mode, when DMDONE is asserted high the data-mover port interface checks for DMREADY low as an
acknowledge. This is equivalent to the mode used in the TSB12LV31 (GPLynx), as shown in Figure 5−31.
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5−31. Data-Mover Handshake Mode (GPLynx Mode)
5.6 Data-Mover Critical Timing
DMCLK
DMDONE
DMRW
DMPRE
DMERROR
PKTFLAG
DMREADY
DMD[0:15]
t
d1
DATA DATAXXXX
t
h0
t
su0
t
su1
t
d2
t
d3
t
d4
XXXX
t
d5
t
d0
t
h1
Figure 5−32. Clock-to-Output Timing With Respect to DMCLK
Table 5−2. CLK-to-Output Timing With Respect to DMCLK
PARAMETER
TERMINAL NAME MIN MAX UNIT
t
d0
DMDONE 1.75 8.5
t
d1
DMRW 1.75 7.5
t
d2
Delay time (DMCLK to Q)
DMPRE 1.75 14.5
ns
t
d3
Delay time (DMCLK to Q)
DMERROR 1.5 11.5
ns
t
d4
PKTFLAG 1.75 8.5
t
d5
DMD[0:15] 0.5 9
t
su0
Setup time to DMCLK
DMREADY 14
ns
t
su1
Setup time to DMCLK
DMD[0:15] 14
ns
t
h0
Hold time from DMCLK
DMREADY 1
ns
t
h1
Hold time from DMCLK
DMD[0:15] 0.75
ns
All timing parameters are referenced to the rising edge of DMCLK.