Datasheet

Data-Mover Port Interface
62
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
5.2.8 Asynchronous Packet Receive With Automatic Header and Trailer Removal
In this mode, when the link receives an asynchronous packet that is addressed to it, the following sequence
of operations is performed.
Step 1: The packet router control logic routes the packet to the data mover. After the headers are sent through,
DMDONE is asserted high for one DMCLK cycle.
Step 2: DMRW is then asserted high as the data payload comes through.
Step 3: After all data has been received on the DMD[0:15] lines, DMRW is asserted low and the trailer quadlet
then comes out on the DMD[0:15] lines.
Figure 5−27 and Figure 5−28 show the timing diagram for this mode for the quadlet receive and the block
receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5−28.
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5−27. Asynchronous Quadlet Receive With Automatic Header and Trailer Removal at 400 Mbps
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5−28. Asynchronous Block Receive With Automatic Header and Trailer Removal at 400 Mbps
5.3 Data-Mover Byte Mode
In this mode the DMD lines are only 1 byte wide when the maximum speed is 200 Mbps. Only the DMD[0:7]
bits are used for the data bus. DMERROR is asserted if transmission of a 400-Mbps packet is attempted.
5.4 Data-Mover Endian Swapping
In this mode the DMD[0:15] bytes are swapped. If the data mover is in byte mode, the least significant byte
is fetched first (see Figure 5−29). If the data mover is not in byte mode, the least significant word is fetched
first and the byte order is then swapped (see Figure 5−30).
01
DMCLK
DMRW
DMD[0:15]
NORM_LINK_DATA
SWAP_LINK_DATA
01020304 A1B2C3D4
04030201 D4C3B2A1
02 03 04 A1 B2 C3 D4
Figure 5−29. Endian Swapping in Byte Mode
0102 0304 A1B2 C3D4
DMCLK
DMRW
DMD[0:15]
NORM_LINK_DATA
SWAP_LINK_DATA
Figure 5−30. Endian Swapping in Word Mode