Datasheet

Data-Mover Port Interface
61
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.2.7 Asynchronous Packet Receive With Headers and Trailer
In this mode, when the link receives an asynchronous packet that is addressed to it, the following sequence
of operations is performed.
Step 1: The packet router control logic routes the packet to the data mover. At the same time, DMDONE is
asserted high for one DMCLK cycle.
Step 2: This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only asserted
high when the header quadlets are being received.
Step 3: After all the data payload has been received on the DMD[0:15] lines, PKTFLAG is asserted high again
as the trailer quadlet is being received. Once the entire packet is received, the DMRW line is asserted
low.
Figure 5−25 and Figure 5−26 show the timing diagram for this mode for the quadlet receive and the block
receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5−26.
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5−25. Asynchronous Quadlet Receive With Headers and Trailer at 400 Mbps
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5−26. Asynchronous Block Receive With Headers and Trailer at 400 Mbps