Datasheet

Data-Mover Port Interface
60
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
5.2.6 Asynchronous Packet Transmit Without Automatic Header Insertion
Upon receiving a high signal on DMREADY from the external logic, the following sequence of operations is
performed.
Step 1: DMDONE is asserted low (deactivated) at the next DMCLK cycle.
Step 2: DMPRE pulses for one DMCLK cycle before the header quadlets are accepted from the external
device on the DM port.
Step 3: The data mover fetches the headers by asserting DMRW high.
Step 4: The data mover then loads the headers into the header0−header3 registers and requests the data
to be transmitted out on the 1394 bus by the link core.
Step 5: The link fetches the headers.
Step 6: DMPRE pulsees for one DMCLK cycle before the first data quadlet is accepted from the external
device on the DM port.
Step 7: The data mover then begins to fetch the data payload by asserting DMRW high.
Step 8: When the link core has fetched the last data quadlet, the data mover waits until the destination node
returns an ack_complete immediate response. If an ack_complete is not received, the data mover
asserts DMERROR high and becomes disabled.
Figure 5−23 and Figure 5−24 show the timing diagram for this mode for the quadlet transmit and the block
transmit cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5−24.
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Header Quadlets
Data Quadlet
Figure 5−23. Asynchronous Quadlet Transmit Without Automatic Header Insertion at 400 Mbps
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Header Quadlets Data Quadlets
Figure 5−24. Asynchronous Block Transmit Without Automatic Header Insertion at 400 Mbps