Datasheet

Data-Mover Port Interface
59
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.2.5 Asynchronous Packet Transmit With Automatic Header Insertion
Upon receiving a high signal on DMREADY from the external logic, the following sequence of operations is
performed.
Step 1: DMDONE is asserted low (deactivated) at the next DMCLK cycle.
Step 2: The data mover takes the headers that have been loaded into the header0−header3 registers and
requests the link core to transmit the data onto the 1394 bus.
Step 3: The link core fetches the headers from the header0−header3 registers.
Step 4: DMPRE pulses for one DMCLK cycle before the first data quadlet is accepted from the external device
on the DM port.
Step 5: The data mover then begin sto fetch the data payload by asserting DMRW high.
Step 6: When the link core has fetched the last data quadlet, the data mover waits until the destination node
returns an ack_complete immediate response. If an ack_complete is not received, the data mover
asserts DMERROR high and becomes disabled.
Figure 5−20, Figure 5−21, and Figure 5−22 show the timing diagram for this mode for the quadlet transmit and
the block transmit cases, respectively. For simplicity, a data block size of three quadlets was selected in
Figure 5−20. Figure 5−22 shows the block transmit case at 400 Mbps.
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5−20. Asynchronous Quadlet Transmit With Automatic Header Insertion
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5−21. Asynchronous Block Transmit With Automatic Header Insertion at 200 Mbps
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5−22. Asynchronous Block Transmit With Automatic Header Insertion at 400 Mbps