Datasheet

Data-Mover Port Interface

SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP

5.2.4 Isochronous Packet Receive With Header and Trailer

In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence of

operations is performed.

Step 1: The packet router control logic routes the packet to the data mover. If the sync bit field in the header

quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port register at 18h, DMPRE

is asserted high for one DMCLK cycle. At the same time, DMDONE is asserted high for one DMCLK

cycle.

Step 2: This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only asserted

high when the header quadlet is being received.

Step 3: After all the data payload has been transmitted on the DMD[0:15] lines, PKTFLAG is asserted high

again as the trailer quadlet is being transmitted. Once the entire packet is transmitted, the DMRW line

is asserted low.

Figure 5−18 shows the timing diagram for this mode at 400 Mbps. Also, Figure 5−18 shows the case where

DMPRE is asserted high for one DMCLK cycle to indicate that the sync bits of the received isochronous header

matches the contents of the ISYNCRCVN field.

DMCLK

DMRW

DMD[0:15]

PKTFLAG

DMDONE

DMPRE

Trailer QuadletHeader Quadlet

Figure 5−18. Isochronous Receive With Header and Trailer

Figure 5−19 shows the timing diagram at 200 Mbps when the received packet contains only one quadlet of

payload.

Packet Payload

0000