Datasheet

Data-Mover Port Interface
57
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.2.3 Isochronous Packet Receive With Automatic Header and Trailer Removal
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence of
operations is performed.
Step 1: The packet router control logic routes the packet to the data mover. If the sync bit field in the header
quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port register at 18h, DMPRE
is asserted high for one DMCLK cycle.
Step 2: After the header is sent through, DMDONE is asserted high for one DMCLK cycle. DMRW is then
asserted high as the data payload comes through.
Step 3: After all data has been transmitted on the DMD[0:15] lines, DMRW is asserted low and the trailer
quadlet then comes out on the DMD[0:15] lines.
PKTFLAG is never asserted high in this mode. Figure 5−17 shows the timing diagram for this mode at
400 Mbps. Figure 5−17 shows the case where DMPRE is asserted high for one DMCLK cycle to indicate that
the sync bits of the received isochronous header match the contents of the ISYNCRCVN field.
Trailer QuadletHeader Quadlet
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
DMPRE
Figure 5−17. Isochronous Receive With Automatic Header and Trailer Removal