Datasheet

Data-Mover Port Interface

SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP

DMCLK

DMRW

DMD[0:15]

DMREADY

DMPRE

DMDONE

Figure 5−15. Isochronous Transmit With Auto Header Insertion at 100 Mbps

5.2.2 Isochronous Transmit Without Automatic Header Insertion

Upon receiving a high on DMREADY, the following sequence of operations is performed.

Step 1: DMDONE is driven low (deactivated) at the next DMCLK cycle.

Step 2: DMPRE pulses for one DMCLK cycle before the first header quadlet is is accepted from lthe external

device.

Step 3: The data mover fetches the header by asserting DMRW high.

Step 4: The data mover then loads the header into the header0 register and requests the data to be

transmitted out on the 1394 bus by the link core.

Step 5: The link fetches the header from the header0 register.

Step 6: DMPRE pulses for one DMCLK cycle before the first data quadlet is is accepted from the external

device.

Step 7: The data mover then begins to fetch the data payload by asserting DMRW high.

Step 8: When the link core has fetched the last data quadlet, the data mover checks the number of channels

specified in the CHNLCNT field in the DM control register to verify whether a data packet has been

sent on each isochronous channel. If all channels have been sent, the data mover waits for a

subaction gap to occur before asserting DMDONE high to indicate the end of the cycle. Otherwise

the data mover provides the header in the next header register and then begins fetching the data

payload until all channels are complete. A data packet must be sent on each active isochronous

channel.

Figure 5−16 shows the timing diagram for this mode at a data transmit rate of 400 Mbps. The dashed sections