Datasheet

Data-Mover Port Interface

SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP

Table 5−1. Modes of Operation

DMASYNC DMHDR DMRX MODE OF OPERATION

0 0 0 Isochronous packet transmit with auto header insertion

0 0 1 Isochronous packet receive with auto header and trailer removal

0 1 0 Isochronous packet transmit without auto header insertion

0 1 1 Isochronous packet receive with header and trailer

1 0 0 Asynchronous packet transmit with auto header insertion

1 0 1 Asynchronous packet receive with auto header and trailer removal

1 1 0 Asynchronous packet transmit without auto header insertion

1 1 1 Asynchronous packet receive with headers and trailer

5.2.1 Isochronous Transmit With Automatic Header Insertion

Upon receiving a high on DMREADY, the following sequence of operations is performed.

Step 1: DMDONE is asserted low (deactivated) at the next DMCLK cycle.

Step 2: The data mover takes the header that has been loaded into the header0 register at 38h and requests

the link core to transmit the data onto the 1394 bus.

Step 3: The link core fetches the header from the header0 register.

Step 4: DMPRE pulses for one DMCLK cycle before the first data quadlet is accepted by GP2Lynx from the

external device.

Step 5: The data mover then begins to fetch the data payload by asserting DMRW high.

Step 6: When the link core has fetched the last data quadlet, the data mover checks the number of channels

specified in the CHNLCNT field in the DM control register at 04h to verify whether a data packet has

been sent on each isochronous channel. If all channels have been sent, the data mover waits for a

subaction gap to occur before asserting DMDONE high to indicate the end of the cycle. Otherwise

the data mover provides the header in the next header register and then begins fetching the data

payload until all channels are complete. A data packet must be sent on each active isochronous

channel.

The timing diagrams in Figure 5−13 through Figure 5−15 illustrate this mode of operation at different transmit

speeds. For simplification, these diagrams show three quadlets of data payload.

DMCLK

DMRW

DMD[0:15]

DMREADY

DMPRE

DMDONE