Datasheet

Data-Mover Port Interface
53
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.1.4.1 Asynchronous Packet Transmit With Automatic Header Insertion
In this mode, the header information is first loaded into the header0−header3 registers through the
microcontroller interface. The headers subsequently are inserted automatically into the data once the data
mover starts streaming data through to the link core transmitter logic. The following steps further illustrate the
process.
Step 1: Asynchronous header quadlets (three quadlets in quadlet mode and four quadlets in block mode) are
loaded into the header0−header3 registers through a write operation from the microcontroller
interface. Loading each header quadlet requires a single write operation.
Step 2: Header quadlets are forwarded to the transmitter of the link core.
Step 3: Packet data (payload only) is transmitted through the data mover directly to the transmitter of the link
core.
Step 4: Asynchronous packet is sent to the 1394 bus through the Phy.
NOTE: The data coming through the data-mover port is typically supplied by an external fast
memory block (i.e., FIFO, DRAM). This external memory logic can begin transmitting data
through to the data-mover port exactly one DMCLK cycle after the DMPRE output pin on the
GP2Lynx is asserted high.
CFR REGISTER
Step 4
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Quadlet#0
Packet Sent to 1394 Bus
Through the Phy
Header1 Register at 3Ch
Quadlet#1
Header2 Register at 40h
Quadlet#2
Header3 Register at 42h
Quadlet#3
Loaded Only in
Block Transmit
Data-
Mover
Port
Step 3 (Packet Data)
Step 2
Step 3
Step 1
Micro-
controller
Interface
Headers
Loaded
Step 1
Write Header
Quadlets
Figure 5−11. Asynchronous Transmit With Auto Header Insertion