Datasheet

Data-Mover Port Interface
49
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.1.2 Isochronous Transmit
There are two ways (modes of operation) to transmit isochronous data through the data mover:
• Isochronous packet transmit with automatic header insertion.
• Isochronous packet transmit without automatic header insertion.
The difference between the two modes lies in the mechanism with which the header information is inserted
into the data stream. However, in both cases the header information is always loaded into the link core
transmitter from the header register starting with the CFR at 38h. There are no trailers for tranmitted packets.
NOTE: With a camera application, if the sync bit field in the isochronous header quadlet needs
to be changed more than once during the transmission of a data block (i.e., one frame), the
header information must be applied manually through the data-mover port.
5.1.2.1 Isochronous Packet Transmit With Automatic Header Insertion
CFR REGISTER
Step 4
Data-
Mover
Port
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Step 2
Step 3
Step 3 (Packet Data)
Packet Sent to 1394 Bus
Through the Phy
Step 1
(Packet Data)
Micro-
controller
Interface
Header
Loaded
Step 1
Write Header
Information
Figure 5−7. Isochronous Transmit With Auto Header Insertion
In this mode, the isochronous header information is first loaded into the Header0 Register at 38h through the
microcontroller interface. Subsequently, the header is inserted automatically into the data once the data mover
starts streaming data through to the link core transmitter logic. The following steps further illustrate the
process.
Step 1: Isochronous header quadlet is loaded into the header0 register at 38h through a write operation from
the microcontroller interface.
Step 2: Header quadlet is forwarded to the transmitter of the link core.
Step 3: Packet data (payload only) is transmitted through the data mover directly to the transmitter of the link
core.
Step 4: Isochronous packet is sent to the 1394 bus through the Phy.
NOTE: The data coming through the data-mover port is typically supplied by an external fast
memory block (i.e., FIFO, DRAM). This external memory logic can begin transmitting data
through to the data-mover port exactly one DMCLK cycle after the DMPRE output pin on the
GP2Lynx is asserted high.