Datasheet

Data-Mover Port Interface
45
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5 Data-Mover Port Interface
The data-mover (DM) port in the TSB12LV32 is the physical medium by which autonomous data streams of
different types are piped to/from an application that uses the TSB12LV32. The DM port is meant to support
an external memory interface that supplies or accepts large data packets.
The DM port can support three types of packets:
• Asynchronous
• Isochronous
• Asynchronous stream packets (1394a-2000 supported format)
The DM port can be configured to either transmit data (asychronous packets or isochronous packets) or
receive data (asychronous and/or isochronous) at one time (half duplex). A typical system diagram is shown
in Figure 5−1.
Application
Phy
Stream Process
(External Memory Interface)
TSB12LV32
µProcessor/µController
(ColdFire)
Data-Mover I/F
Microcontroller Interface
Phy/Link I/F
Figure 5−1. A Typical System Diagram
The DM port performs all operations synchronously, using a 24.576-MHz output clock called DMCLK. DMCLK
is essentially SCLK/2. There is no asynchronous logic within the DM block. All data transfers are synchronized
to the DMCLK output. The DM operates by setting the DM control CFR at 04h and the control CFR at 08h.
The DM logic module interfaces internally with the configuration register (CFR) block and the link core (Link)
block and interfaces externally with the data-mover external interface.
The advantages of the DM port can be summarized as follows:
• Transmits or receives large blocks of data at speeds up to 400 Mbps.
• Allows for a large external FIFO specific to an individual application.
• Handles asynchronous, isochronous, or asynchronous stream packets.
• The DM interface goes to the high-impedance-state when not in use.
The DM isochronous transmit reads data from the DM interface (DMD[0:15] lines) and passes it to the 1394
isochronous transmit interface in accordance with Figure 5−2. The data path is shown in Figure 5−3.