Datasheet

Link Core
42
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
4.4 Cycle Timer
The cycle timer is only used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as defined
by the IEEE 1394-1995 specification. In the TSB12LV32, the cycle-timer register is implemented in the cycle
timer located in the IEEE 1212 initial register space at location 200h and can also be accessed through the
local bus at TSB12LV32 CFR address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which
increments once every 24.576-MHz clock period (or 40.69 ns). The next 13 higher-order bits are a count of
8,000 Hz (or 125 µs) cycles, and the highest 7 bits count seconds. The cycle timer contains the cycle-timer
register. The cycle-timer register consists of three fields: cycle offset, cycle count, and seconds count. The
cycle timer has two possible sources. First, when the cycle source (CYSRC) bit in the configuration register
(bit 21 of the control CFR at 08h) is set, then the CYCLEIN input terminal causes the cycle count field to
increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros.
CYCLEIN should only be the source when the node is the cycle master. The timer can also be disabled using
the cycle-timer-enable bit (CYTEN) in the control register. The second cycle-source option is when the CYSRC
bit is cleared. In this state, the cycle-offset field of the cycle-timer register is incremented by the internal
24.576-MHz clock. The cycle timer is updated by the reception of the cycle-start packet for the noncycle
master nodes. The cycle-offset field in the cycle-start packet is used by the cycle-master node to keep all
nodes in phase and running with a nominal isochronous cycle of 125 µs. The cycle-start bit is set when the
cycle-start packet is sent from the cycle master node or received by a noncycle master node.
4.5 Cycle Monitor
The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
device activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cyclemaster bit (CYMAS) is set in the control register.
4.6 Cyclic Redundancy Check (CRC)
The CRC module generates a 32-bit CRC for error detection. This is done for both the header and the data.
The CRC module generates the header and data CRC for transmitting packets and checks the header and
data CRC for received packets (see the IEEE 1394-1995 standard for details on the generation of the CRC).
4.7 Received Packet Routing Control Logic
Asynchronous and isochronous receive packets can be routed to the DM port or the GRF depending on the
setting of the receiver routing control logic. Bit IRCVALL in the isochronous port CFR at 18h must be set for
all isochronous data to be routed according to Table 4−1. Note that self-ID packets and Phy packets are always
received by the GRF regardless of the routing control settings.