Datasheet

Link Core

SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP

4 Link Core

This section describes the link core components and operations. Figure 4−1 shows the link core components.

Transmitter

Cycle Timer

Cycle Monitor

CRC

Receiver

Physical

Interface

Figure 4−1. Link Core Components

4.1 Physical Interface

The physical (Phy) interface provides Phy-level services to the transmitter and receiver. This includes gaining

access to the serial bus, sending packets, receiving packets, and sending and receiving acknowledge

packets. The Phy interface module also interfaces to the Phy chip and implements Texas Instruments

patent-pending bus-holder galvanic isolation.

4.2 Transmitter

The transmitter retrieves data from either the asynchronous transmit FIFO (ATF) or the data-mover (DM) port

and creates correctly formatted 1394 packets to be transmitted through the Phy interface. When data is

present at the ATF interface to the transmitter, the TSB12LV32 Phy interface arbitrates for the 1394 bus and

sends an asynchronous packet. When data is present at the DM port, the TSB12LV32 requests bandwidth

during the next isochronous cycle from the 1394 bus isochronous resource master if the packet is isochronous

or arbitrates for the 1394 bus if the packet is asynchronous. The transmitter autonomously sends the

cycle-start packets when the device is a cycle master.

4.3 Receiver

The receiver takes incoming data from the Phy interface and determines if the incoming data is addressed

to the node. When the incoming packet is addressed to the node, the CRC of the packet is checked. If the

header CRC is good, the header is confirmed in the general receive FIFO (GRF). For asynchronous stream

packets and isochronous packets, the remainder of the packet is confirmed one quadlet at a time. The receiver

places a status quadlet in the GRF after the last quadlet of the packet is confirmed into the GRF. The status

quadlet contains the error code for the packet.

In the case of asynchronous packets, the error code is the acknowledge code that is sent (returned) for that

packet. For isochronous and broadcast packets that do not need acknowledge packets, the error code is the

acknowledge code that would have been sent. This acknowledge code tells the transaction layer whether or

not the data CRC is good or bad. If the header CRC is bad, the header is flushed and the rest of the packet

is ignored. When a cycle-start packet is received, it is detected and the cycle-start packet data is sent to the

cycle timer. Cycle-start packets are not placed in the GRF like other quadlet packets.