Datasheet
Microcontroller Interface
39
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
Table 3−4. Endian Swapping Operations
LENDIAN M8BIT/SIZ0 MDINV DESCRIPTION
0 X X Big-endian mode, no manipulation on byte address and data bytes
1 1
(8-bits wide)
1 Little-endian data invariance mode, swap the low order 2 bit address:
External low-order 2-bit address Internal low order 2-bit address
Byte Address 00
↔ Byte Address 11
Byte Address 01
↔ Byte Address 10
Byte Address 00
↔ Byte Address 11
Byte Address 11 ↔ Byte Address 00
1 01
(16-bits wide)
1 Little-endian data invariance mode, swap the low order 2 bit address:
External low-order 2-bit address Internal low order 2-bit address
Word Address 00
↔ Word Address 10
Word Address 10
↔ Word Address 00
1 1 0 16-bit little-endian address invariance mode, swap data between MD[0:7] and MD[8:15].
1 1 0 8-bit little-endian address invariance mode, no manipulation on byte address and data bytes.
Because the TSB12LV32 microprocessor interface is either 8 bits or 16 bits wide, but the internal configuration
registers are 32 bits wide, a byte stacking (for writes) and a byte unstacking (for reads) operation must be
performed on the data bus. For little endian processors, the TSB12LV32 can perform the swapping of bytes
on the data bus required to allow both the processor and the TSB12LV32 to interpret the data the same. There
are two methods of swapping the data bytes, address invariant and data invariant. Both of these methods are
described in the following sections.
NOTE: For the host processor to work correctly with the TSB12LV32, users must correctly
connect the address and data busses of their microprocessor to the TSB12LV32
microprocessor port. Users must connect the MSB (most significant bit) of their address/data
bus to the address/data MSB of the TSB12LV32. This must be done regardless of bit number
labeling or which type of endianness the microprocessor uses.
3.3.5.2 Data-Invariant System Design
Figure 3−18 shows a little-endian data-invariant system design example. In this system, the actual value of
the data as it was stored in the processor memory is preserved. Data-invariant designs do not preserve the
addresses when mapping between endian domains. If the data represents an integer, it is interpreted the same
by both systems. If the data represents a string, an array, or some other type of byte indexed structure, it is
interpreted differently by both systems.
aa
Byte 3
(MSByte)
Little Endian Processor Memory
dd
(MSByte)
Byte 0
TSB12LV32 CFR/Memory
bb
Byte 2
cc
Byte 1
cc
Byte 1
bb
Byte 2
dd
Byte 0
(LSByte)
aa
(LSByte)
Byte 3
Figure 3−18. Little-Endian Data-Invariance Illustration Chart
3.3.5.3 Address Invariant System Design
Figure 3−19 shows a little-endian address-invariant system design example. In this case, the byte ordering
between both systems is preserved (i.e., byte address is preserved). For example, byte 3 in the little-endian
processor memory is also byte 3 in the TSB12LV32 CFR space. As Figure 3−19 shows, the byte ordering is
automatically maintained by the TSB12LV32 when in the address-invariance mode by swapping the order in
which the incoming bytes on the microprocessor are written to the CFRs.