Datasheet

Microcontroller Interface
38
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
Table 3−3. Microcontroller Timing
PARAMETER
†
TERMINAL NAME ACCESS TYPE MIN MAX UNIT
t
d0
MCA Read/Write 3.75 9.5
t
d1
Delay time (BCLK to Q)
TEA Read/Write 3.75 9.5
ns
t
d2
Delay time (BCLK to Q)
MD[0:15] Read 2.5 10.5
ns
t
su0
MWR Read/Write 4.5
t
su1
MCS Read/Write 6.5
t
su2
Setup time to BCLK
MA[0:6] Read/Write 6.5
ns
t
su3
Setup time to BCLK
M8BIT/SIZ0 Read/Write 5
ns
t
su4
MCMODE/SIZ1 Read/Write 3.5
t
su5
MD[0:15] Write 3
t
h0
MWR Read/Write 1.75
t
h1
MCS Read/Write 1.5
t
h2
Hold time from BCLK
MA[0:6] Read/Write 2
ns
t
h3
Hold time from BCLK
M8BIT/SIZ0 Read/Write 1.5
ns
t
h4
MCMODE/SIZ1 Read/Write 1.75
t
h5
MD[0:15] Write 1.5
†
All timing parameters are referenced to the rising edge of BCLK.
3.3.5 Endian Swapping
The term endianness refers to the way data is referenced and stored in a processor’s memory. For example,
consider a 32-bit processor; any 32-bit word consists of four bytes which can be stored in memory in one of
two ways. Of the four bytes, either byte 3 is considered the most significant byte and byte 0 the least significant
byte, or vice versa (see Figure 3−16 and Figure 3−17). A little endian type memory considers byte 0 the least
significant byte, whereas a big endian type memory considers byte 3 to be the least significant byte.
Byte #0
(Most Significant Byte)
Byte #1 Byte #2
Byte #3
(Least Significant Byte)
Figure 3−16. Big Endian Format
Byte #3
(Most Significant Byte)
Byte #2 Byte #1
Byte #0
(Least Significant Byte)
Figure 3−17. Little Endian Format
The TSB12LV32 configuration register space (CFR) and FIFO memory, both of which are 32 bits wide, use
a big endian architecture. The TSB12LV32 uses the same endianness as the internal 1394a-2000 link core.
This means that the most significant byte is the left-most byte (byte 0) and the least significant byte is the
right-most byte (byte 3).
3.3.5.1 Data and Address Invariance for Little Endian Processors
For little-endian processors, there are two modes of byte swapping, address invariant and data invariant.
Address invariance preserves byte ordering between the internal system (GP2Lynx registers and FIFO) and
external system (microcontroller/processor). Data invariance preserves the bit significance of the data, but
changes the byte significance between the internal and external systems. The MDINV pin controls how the
write/read data is swapped at the data bus (i.e., determines how the received bytes from the microcontroller
are mapped into the TSB12LV32 internal registers and memory space). Note that when the COLDFIRE pin
is high, the MDINV pin has no affect and data is always interpreted as big endian. See Endianness and the
TSB12LV41 (MPEG2Lynx) Microprocessor Interface, Texas Instruments literature number SLLA021, for a
detailed description of endianness.
The pin settings for all the swapping operations are shown in Table 3−3. Note that in performing the byte
swapping operation in the little-endian mode, only the two least significant bits of the 32-bit address inside are
involved. This is because there is a total of four bytes associated with the swapping operation.