Datasheet

Microcontroller Interface
35
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
3.3.3 Microcontroller ColdFire Mode
The TSB12LV32 supports a glueless interface to the ColdFire family of microcontrollers. To enable this mode,
the COLDFIRE pin must be asserted and kept high for the entire access cycle. The timing diagram for a
ColdFire read operation is shown in Figure 3−13.
The timing sequence for a ColdFire read access can be summarized as follows:
1. The ColdFire pulses MCS
low for one BCLK cycle to signal the start of access. MCS must only be asserted
for one clock cycle.
2. When the rising edge of BCLK samples MCS
low and MWR high, MD lines are enabled, but do not yet
contain valid data. The MA lines should contain the address information at this point. MA is only required
to be available for one BCLK cycle. The data transfer size is determined by the state of the MCMODE/SIZ1
and M8BIT/SIZ0 lines.
3. The TSB12LV32 pulses MCA
low for n clock cycles to signal the requested operation is complete. The
number n depends on the data transfer size specified by the MCMODE/SIZ1 and M8BIT/SIZ0 lines. The
CFR register value or GRF memory data pointed to by the MA lines is latched onto the MD lines. MCA
pulses for one clock cycle on every word (2 byte) transfer.
The microinterface uses burst transfers if the MCMODE/SIZ1 and M8BIT/SIZ0 lines indicate more than
2 bytes (1 word) of data. The TSB12LV32 does not support 1-byte transfers in the ColdFire mode.
MCMODE/SIZ0 M8BIT/SIZ1 TRANSFER SIZE
(BYTES)
0 0 4
0 1 2
1 0 1*
1 1 0
* A transfer size of 1 byte is not valid and TEA is asserted lo for one BCLK cycle.
If any transfer error condition occurs, TEA is asserted low for one BCLK cycle. An error condition can occur
if the MCMODE/SIZ1 and M8BIT/SIZ0 lines specify a transfer size of 1 byte or if their state changes during
the access cycle. Note that all 16 bits of the MD lines are always used in the ColdFire mode.