Datasheet

Microcontroller Interface
32
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
Byte fixed-timing write and word fixed-timing write are shown in Figure 3−9 and Figure 3−10, respectively.
Unlike the fixed-timing read transfers, no extra wait cycles are required for fixed-timing write transfers. For an
8-bit data bus, MD[0:7] is not used (don’t care) and is driven with zeros. If the write transaction is accessing
a CFR register, it cannot cross any register boundary. The first write data for each ATF quadlet must start at
byte0. Write accesses to the ATF must be quadlet aligned. The microcontroller interface waits for all bytes of
each quadlet to be available before creating a write request to the ATF. If a transfer error condition occurs,
TEA
is asserted low for one BCLK cycle. An error condition can occur if the MCMODE/SIZ1 or M8BIT/SIZ0
lines transition during the access cycle.
BCLK
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A0 A1 A2
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
Figure 3−9. Byte Fixed-Timing Write