Datasheet

Microcontroller Interface
30
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
BCLK
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A2 A3A1A0
D4 D6D2D0
D5 D7D3D1
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
Figure 3−6. Word Handshake Write
3.3.2 Microcontroller Fixed-Timing Mode
Byte fixed-timing reads and word fixed-timing reads are shown in Figure 3−7 and Figure 3−8, respectively.
In addition to single byte or single word transfers, fixed-timing mode supports burst transfers. If MCS
is
asserted low for more than one BCLK cycle, burst mode is enabled. The fixed-timing burst mode does not have
a limit on the maximum burst size allowed.
The signal timing sequence for a fixed-timing read transaction can be summarized as follows:
1. The microcontroller pulses MCS
low to signal the start of access. Pulsing MCS low for more than one clock
cycle enables burst mode. The number of BCLK cycles during which MCS
is asserted low determines the
total burst size.
2. When the rising edge of BCLK samples MCS
low and MWR high, the register value or GRF data pointed
to by the MA bus is latched onto the MD lines. The MD lines latch on every rising edge of BCLK if MCS
continues to be asserted low. The first data transfer of each fixed-timing read (single byte/word or burst)
requires one extra BCLK cycle due to propagation delay in the device. In the case of a burst data transfer,
all subsequent reads require only one BCLK cycle. The data on the MD bus is valid when MCA
is low.
3. After 2 BCLK cycles, the TSB12LV32 pulses MCA
low for one clock cycle to signal the completion of the
requested operation. If MCS
is pulsed low for n BCLK cycles, MCA also is pulsed low for n cycles. Note
that MA needs only contain valid data during the first cycle in which MCS
is low. Except for the first one,
every data transfer takes only one BCLK cycle. If a read transaction is accessing the CFR, it may not cross
any register boundary (see Section 3.3.2.1 for information on fixed-timing read access to the GRF). During
a burst read or a burst write, the initial latched address on the MA bus is automatically incremented by
the hardware for each additional read or write, and the value on the MA bus is ignored until the next
transfer.
After MCA
is asserted high, another read or write transaction can begin after the next rising edge of BCLK.
Note that data size is determined by the M8BIT/SIZ0 signal, it is asserted high to indicate a byte transfer and
it is asserted low to indicate a word transfer. The MCMODE/SIZ1 signal is asserted low to select fixed timing
mode.