Datasheet
Microcontroller Interface
29
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
Byte handshake write and word handshake write are shown in Figure 3−5 and Figure 3−6. In this case, the
microcontroller interface asserts MCA
low immediately after MCS is sampled low. The data on the MD bus
is valid when MCS
and MWR are both low. The microcontroller interface keeps MCA low until it samples MCS
high. For 8-bit accesses, the MD[0:7] lines are not used. If a transfer error condition occurs, TEA is asserted
low for one BCLK cycle. An error condition can occur if the MCMODE/SIZ1 or M8BIT/SIZ0 line changes state
during the access cycle.
BCLK
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A2 A3A1A0
D2 D3D1D0
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
Figure 3−5. Byte Handshake Write