Datasheet

Internal Registers
23
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
2.2.17 Trailer Register at 48h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
NUMBER OF QUADLETS ACKCODE
SPD
LPS_RESET
LPS_OFF
The power-up reset value of this register equals 0000 0000h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0−1 RESERVED Reserved
2−15 NUMBER OF
QUADLETS
Number of
quadlets
R/W Total number of quadlets in the current packet (data payload and header quadlets only)
16−18 RESERVED Reserved
19−23 ACKCODE Acknowledge
code
R/W
This 5-bit field holds the acknowledge code sent by the receiver for the current packet
(see Note following the table):
code
ACKCODE Name
00000 Reserved
00001 Ack_complete
00010 Ack_pending
00011 Reserved
00100 Ack_busy_X
00101 Ack_busy_A
00110 Ack_busy_B
00111–01010
01011
01100
Reserved
Ack_tardy
Ack_conflict_error
01101 Ack_data_error
01110 Ack_type_error
01111 Ack_address_error
10000 No ack received
These codes are added by the link layer and
are not part of the IEEE 1394−1995
10001 Ack too long
(more than 8 bits)
These codes are added by the link layer and
are not part of the IEEE 1394−1995
specification.
10010 Ack too short
(less than 8 bits)
10011−11111 Reserved
24−25 RESERVED Reserved
26−27 SPD Speed code R/W The SPD field indicates the speed at which the current packet was sent.
00 ≥ 100 Mbps, 10 ≥ 400 Mbps,
01 ≥ 200 Mbps, 11 is undefined.
28 − 29 RESERVED Reserved
30 LPS_RESET LPS reset R/W Link power status reset. This bit is set by software and is reset by hardware. When this
bit is set, hardware deactivates LPS for a fixed period to ensure that the Phy has reset
the interface. It then reactivates LPS. When this bit is cleared by hardware, a PHRST
interrupt in the interrupt CFR at 0Ch is also generated.
31 LPS_OFF LPS off R/W Link power status off. If set to 1, this bit turns off the LPS-pulsed output to the Phy. This
bit can also be turned off from the Phy. Upon detection of the LINKON pulsed input
signal, this bit is turned off, allowing LPS to be driven to the Phy which, in turn, activates
SCLK and powers up the link.
NOTE: The acknowledge code specified by the IEEE 1394-1995 specification is a 4-bit field.
The ACKCODE field in this register is a 5-bit field. The TSB12LV32 logic core is able to provide
(specifiy) three additional ACKCODEs, which are not part of the original specification. The
ACKCODEs are 10000, 10001, and 10010.