Datasheet

Internal Registers

SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP

2.2.16 Header3 Register at 44h

Header3 register contains the isochronous packet header (if multiple channels are supported) or the fourth

quadlet of an asynchronous packet header if the device is in automatic-header-insert transmit mode. If the

device is not in automatic-header-insert mode or if it is in receive mode, this register is updated with the fourth

quadlet of the asynchronous received header or DM-supplied transmit header. This register powers up with

all bits reset to 0. For multiple isochronous channels (multiple isochronous packets within the same

isochronous cycle), this register would contain the isochronous header of the fourth isochronous packet in the

same format as the header0 register if the device is in automatic-header-insert transmit mode. This register

is write protected such that it cannot be written to unless automatic-header-insert mode is enabled and the

DM is in transmit mode (i.e., DMHDR = 0 and DMRX = 0).

ISOCHRONOUS HEADER FOR QUADLET 3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS

BIT

NUMBER

BIT NAME FUNCTION DIR DESCRIPTION

0−15 PACKET DATA

LENGTH

Packet data length R/W Packet data length in bytes

16−17 TAG Tag field R/W The tag field provides a high-level label for the format of the data carried

by the isochronous packet.

18−23 CHANNEL NUMBER Channel number R/W Channel number field

24−27 TCODE Transmission code R/W Packet transaction code

28−31 SYNC BITS Synchronization

code

R/W An application-specific control field

ASYNCHRONOUS HEADER FOR QUADLET 3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31

HEADER3

BIT

NUMBER

BIT NAME DIR DESCRIPTION

0−31 Header3 R/W Fourth header quadlet for an asynchronous packet or header for a multiple isochronous packet