Datasheet

Internal Registers
19
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
2.2.12 Bus Reset Register at 34h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
NRIDVAL
NODECNT
ROOT
CONTENDER
IRMNODEID BUS NUMBER NODE NUMBER
The power-up reset value of this register equals 81BF FFC0h.
NOTE: The power-up reset value shown above assumes one node on the bus only. A
1394a-2000 compliant Phy is assumed to be attached to the TSB12LV32. If a 1394-1995 Phy
is attached to the TSB12LV32 link, the NODECNT filed is 0. This is due to the fact that a
1394-1995 compliant Phy does not report its self-ID packet back to the local link.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0 NRIDVAL Valid R When set, NRIDVAL indicates that the node ID, IRM node ID, node count, and root
information are valid. This bit is read-only.
1 RESERVED Reserved
2−7 NODECNT Node count R NODECNT contains the number of nodes detected in the system. This field is loaded
with 1 following a power-on reset. The NODECNT field is read-only.
8 ROOT Root R Root is set when the current node is the root node. This bit is read-only.
9 CONTENDER Contender R Contender contains the status of the TSB12LV32 CONTNDR terminal. This bit is read-
only.
10−15 IRMNODEID IRM node
identification
R IRMNODEID is the isochronous resource manager node identification. If there is no
IRM node present on the bus, these bits are equal to 3Fh. These bits are read-only.
16−25 BUS NUMBER Bus number R/W BUSNUMBER is the 10-bit IEEE 1212 bus number. These bits are set to 3FFh when the
BUSNRST bit in the control CFR at 08h is set and there is a bus reset.
26−31 NODE
NUMBER
Node number R/W NODENUMBER is the node number of the current node. These bits are automatically
updated following a bus reset. To change the node number of this node (spoofing), the
TESTMODE terminal must be set high. Spoofing is used for TI internal test purposes
only.
2.2.13 Header0 Register at 38h
Header0 register contains the isochronous packet header or the first quadlet of an asynchronous packet
header if the device is in automatic-header-insert transmit mode. If the device is not in automatic-header-insert
transmit mode or if it is in receive mode, this register is updated with the received header or the DM-supplied
transmit header. This register is write protected such that it cannot be written to unless automatic header insert
mode is enabled and the DM is in transmit mode (i.e., DMHDR = 0 and DMRX = 0). The power-up reset value
of this register equals 0000 0000h.
ISOCHRONOUS HEADER FOR QUADLET 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31
28
PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0−15 PACKET DATA
LENGTH
Packet data
length
R/W Packet data length in bytes.
16−17 TAG Tag field R/W The tag field provides a high-level label for the format of the data carried by
the isochronous packet.
18−23 CHANNEL
NUMBER
Channel number R/W Channel number field
24−27 TCODE Transmission
code
R/W Packet transaction code
28−31 SYNC BITS Synchronization
code
R/W An application-specific control field