Datasheet

Internal Registers
18
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
2.2.11 FIFO Status Register at 30h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
ATFCLR
ATFFULL
ATFWBMTY
GRFEMPTY
GRFCLR
ATFAVAIL
CD
ATACK GRFUSED
The power-up reset value of this register equals 6083 0000h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0 ATFCLR ATF clear R/W ATF clear. When this bit is set to 1, the ATF is cleared. This bit clears itself.
1 ATFWBMTY ATF write
buffer empty
R ATF write buffer empty. This bit is set when the 4-quadlet ATF write buffer is empty.
2−11 ATFAVAIL ATF space
available
R Size of ATF available, in quadlets. The power-on value of this field is 10 0000 1000 (520
quadlets).
12 ATFFULL ATF full bit R When the ATF is full, this bit is set.
13 GRFCLR GRF clear bit R/W GRF clear. Set this bit to 1 to clear the contents of the GRF. This bit clears itself.
14 RESERVED Reserved
15 GRFEMPTY GRF empty R GRF empty. GRFEMPTY is set when the four-quadlet GRF read buffer is empty and the
GRF is empty too.
16 CD Check 33
rd
bit
(GRF read)
R This bit is set to 1 when the quadlet pointed to by the GRF read pointer is the first quadlet
or the packet trailer (packet token).
17−21 ATACK ATF
acknowledge
R The acknowledge received in response to a packet sent via the ATF
22−31 GRFUSED GRF space
used
R GRF space used, in quadlets. This value is the number of quadlets written in the GRF.
This does not count the entire read buffer, which can hold five quadlets. If the GRF is
empty and the microcontroller attempts to read the GRF, the last quadlet in the GRF is
reread.