Datasheet

Internal Registers
16
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
2.2.8 Diagnostic Register at 20h
B3_PND
0123456789101112131415161718192021222324252627 29303128
B2_BUSY B3_BUSY
B0_PND
B1_PND B2_PND
RAMTEST
REGRW
B0_BUSY B1_BUSY
STATESEL0 STATESEL1 STATESEL2
The power-up reset value of this register equals 0000 4AD0h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0 B0_BUSY Byte 0 busy R Byte 0 busy. When this bit is set, no microcontroller write to byte 0 of any CFRs is allowed.
The microcontroller must first poll this bit before writing to byte 0.
1 B1_BUSY Byte 1 busy R Byte 1 busy. When this bit is set, no microcontroller write to byte 1 of any CFRs is allowed.
The microcontroller must first poll this bit before writing to byte 1.
2 B2_BUSY Byte 2 busy R Byte 2 busy. When this bit is set, no microcontroller write to byte 2 of any CFRs is allowed.
The microcontroller must first poll this bit before writing to byte 2.
3 B3_BUSY Byte 3 busy R Byte 3 busy. When this bit is set, no microcontroller write to byte 3 of any CFRs is allowed.
The microcontroller must first poll this bit before writing to byte 3.
4 B0_PND Byte 0
pending
R Byte 0 pending. When this bit is set, it indicates that byte 0 of a word or quadlet write has been
accepted and the hardware is waiting for the remaining bytes to be written. When the full write
is complete, this bit is cleared.
5 B1_PND Byte 1
pending
R Byte 1 pending. When this bit is set, it indicates that byte 1 of a word or quadlet write has been
accepted and the hardware is waiting for the remaining bytes to be written. When the full write
is complete, this bit is cleared.
6 B2_PND Byte 2
pending
R Byte 2 pending. When this bit is set, it indicates that byte 2 of a word or quadlet write has been
accepted and the hardware is waiting for the remaining bytes to be written. When the full write
is complete, this bit is cleared.
7 B3_PND Byte 3
pending
R Byte 3 pending. When this bit is set, it indicates that byte 3 of a word or quadlet write has been
accepted and the hardware is waiting for the remaining bytes to be written. When the full write
is complete this bit is cleared.
8 RAM_TEST Internal test R/W This bit can be set only when TESTMODE is high. When this bit is set, the built-in self-test
(BIST) for the FIFOs (transmit and receive) is run. On completion of the test hardware resets
this bit to 0 and simultaneously sets bits 30 and 31. This is for TI internal test purposes only.
9 REGRW Register
read/write
access
R/W When REGRW is set, write-protected bits in various registers can be written (particularly in
the interrupt / interrupt mask registers).
10−15 RESERVED Reserved
16−19 STATSEL0 State0
select
R/W Status output select bits. Used to program the output of STAT0 terminal. See Table 1−2.
20−23 STATSEL1 State1
select
R/W Status output select bits. Used to program the output of STAT1 terminal. See Table 1−2.
24−27 STATSEL2 State2
select
R/W Status output select bits. Used to program the output of STAT2 terminal. See Table 1−2.
28−31 RESERVED Reserved