Datasheet

Internal Registers
13
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
BIT
NUMBER
DESCRIPTIONDIRFUNCTIONBIT NAME
14 SNTRJ Busy
acknowledge
sent by receiver
R/W When SNTRJ is set, the receiver is forced to send a busy acknowledge to any packet
addressed to this node because the GRF overflowed.
15 HDRERR Header error R/W When HDRERR is set, the receiver detected a header CRC error on an incoming
packet that may have been addressed to this node. Any packet with a CRC error is
discarded.
16 TCERR Transaction
code error
R/W When TCERR is set, the transmitter detected an invalid transaction code in the data at
the transmit-FIFO interface.
17 DMACKERR Data-mover
acknowledge
error
R/W DM acknowledge error. This bit is set to 1 when the acknowledge received is not ack
complete. When this occurs, DMEN (bit 26) of the DM control CFR at 04h is reset to 0
and no more asynchronous transmissions from the DM port are allowed to take place
until DMEN is set to 1.
18 FIFOACK FIFO
acknowledge
interrupt
R/W FIFO ack interrupt. This bit is set when an acknowledge from a previous ATF
transmission has been received.
19 MCERROR Microcontroller
interface error
R/W Microcontroller interface error. This bit is set whenever the microcontroller write
protocol is violated. This bit is set to 1 when read or write errors occur on the
microcontroller interface. This bit latches the value on the TEA
signal terminal. This
interrupt is set one clock cycle after the triggering error occurs.
20 CYSEC Cycle second
incremented
R/W When CYSEC is set, the cycle-second field in the cycle timer register has incremented.
This occurs about every second when the cycle timer is enabled.
21 CYST Cycle started R/W When CYST is set, the transmitter has sent or the receiver has received a cycle-start
packet.
22 CYDNE Cycle done R/W When CYDNE is set, a subaction gap has been detected on the bus after the
transmission or reception of a cycle-start packet. This bit indicates that the isochronous
cycle is complete.
23 RESERVED Reserved
24 CYLST Cycle lost R/W When CYLST is set, the cycle timer has rolled over twice without the reception of a
cycle-start packet. This occurs only when this node is not the cycle master. All
isochronous traffic stops once CYLST is set. However, asynchronous and
asynchronous stream packet traffic is not affected.
25 CARBFL Cycle
arbitration failed
R/W When CARBFL is set, the arbitration to send a cycle-start packet has failed.
26 ARBGP Arbitration gap R/W When ARBGP is set, the 1394 bus has been idle for an arbitration reset gap.
27 SUBGP Subaction gap R/W When SUBGP is set, the 1394 bus has been idle for a subaction gap time (fair gap). This
bit can be set only when the REGRW bit has been set in the diagnostics CFR at 20h.
28−30 RESERVED Reserved
31 IARBFL Isochronous
arbitration failed
R/W When IARFL is set, the arbitration to send an isochronous packet has failed.
2.2.5 Cycle Timer Register at 14h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
SECONDS COUNT CYCLE OFFSETCYCLE COUNT
This register must be written to as a quadlet. The power-up reset value of this register equals 0000 0000h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0−6 SECONDS
COUNT
Seconds count R/W 1-Hz cycle timer counter
7−19 CYCLE
COUNT
Cycle count R/W 8,000-Hz cycle timer counter
20−31 CYCLE
OFFSET
Cycle offset R/W 24.576-MHz cycle timer counter