Datasheet
Internal Registers
12
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
2.2.4 Interrupt/Interrupt Mask Registers at 0Ch and 10h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
PHINT
SELFIDEND
ATSTARTED
SELFIDER
RXDMPKT
PHRRX
SNTRJ
CYDNE
CYSEC
CYST
CYLST
CARBFL
IARBFL
ARBGP
SUBGP
HDRERR
INT
ATFEMPTY
PHRST
CMDRST
DMERROR
RXGRFPKT
ATSTK
TCERR
MCERROR
DMACKERR
FIFOACK
LINKON
The interrupt and interrupt mask register work in tandem to inform the microcontroller interface when the state
of the TSB12LV32 changes. The interrupt register is at 0Ch and the interrupt mask register is at 10h. The
interrupt register powers up all 0s, however, the interrupt mask register powers up with the INT and the
MCERROR bits set, i.e., 8000 1000h. The mask bits allows individual control for each interrupt. A 1 in the mask
bit field allows the corresponding interrupt in the interrupt register to be generated. Once an interrupt is
generated it must be cleared by writing a 1 to the bit in the interrupt register. For testing, each interrupt bit can
be set manually. This is done by first setting the REGRW bit in the diagnostic register at 20h and then setting
the individual interrupt bit. This is also true for bit 0 in the interrupt register. In this test mode, the interrupt mask
register is not used and has no effect.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0 INT Interrupt R/W INT contains the value of all interrupt and interrupt mask bits ORed together.
1 PHINT Phy chip
interrupt
R/W When PHINT is set, the Phy has signalled an interrupt through the Phy interface
2 PHRRX Phy register
information
received
R/W When PHRRX is set, a register value has been transferred to the Phy access register
(CFR at offset 24h) from the Phy interface.
3 PHRST Phy reset
started
R/W When PHRST is set, a Phy-LLC reconfiguration has started (1394 bus reset).
4 SELFIDEND Self-ID
validated
R/W Self-ID end. This bit is set at the end of the self-ID reporting process. When this bit is set,
the contents of the bus reset CFR at 34h are valid. The RXSID bit must be set to 1 for the
SELFIDEND interrupt to function.
5 ATSTARTED Asynchronous
transfer started
R/W Asynchronous transfer started. This bit is activated when the 1394 bus has been
granted and the first quadlet from the FIFO is about to be transmitted from the ATF.
6 RXGRFPKT GRF packet
received
R/W Receive packet to GRF. This bit is set whenever a complete packet has been confirmed
into the GRF (asynchronous or isochronous).
7 CMDRST CSR register
reset request
R/W If the CMDRST bit is set, the device has been sent a quadlet write request to the
Reset_Start CSR register (target address is FFFF F000 000Ch).
8 DMERROR Data-mover
error
R/W DM error. This bit is set if there is an error in the DM stream.
For transmit, if the DM port is configured for byte access and the speed code in the DM
control register or the asynchronous header register is set for 400 Mbps, then this bit is
set. Under this condition DMEN (bit 24 of the DM control CFR at 04h) is reset to 0,
preventing further transmit.
For receive this bit is set if there is a header or data CRC error or if the DM port is
configured for byte access and the data is received at 400 Mbps. Any packet with a
CRC error is discarded.
9 RXDMPKT Data-mover
packet receive
R/W Receive packet to DM. This bit is set whenever a packet is received to the DM port.
10 SELFIDER Self-ID packet
error
R/W This bit is set if an error in the self-ID quadlet/packet has been detected.
11 LINKON Link-ON detect R/W This bit is set if a link-on pulse is detected on the LINKON input terminal. This bit should
be used by software to reactivate the LPS output to the Phy.
12 ATSTK Transmitter is
stuck (AT)
R/W When ATSTK is set, the transmitter has detected invalid data at the asynchronous
transmit-FIFO interface. If the first quadlet of a packet is not written to the ATF_First or
ATF_First&Update or there is an underflow of the ATF, an ATSTK interrupt is generated.
When this state is entered, no asynchronous packets can be sent until the ATF is
cleared by way of the ATFCLR control bit in the FIFO status CFR at 30h. Isochronous
packets can be sent while in this state.
13 ATFEMPTY ATF empty
interrupt
R/W ATFEMPTY. This bit is set to 1 when the ATF becomes empty.