Datasheet

Internal Registers
11
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
BIT
NUMBER
DESCRIPTIONDIRFUNCTIONBIT NAME
15 BUSNRST Bus number
reset enable
R/W When this enable is set high, the bus number field in the bus reset CFR at 34h clears
to 3FFh when a local 1394 bus reset is received.
16−17 BDIV0, BDIV1 BCLK divisor
encode bits
R/W BCLK divisor encode bits. Used to divide down the BCLK to generate the link power
status (LPS) clock to the Phy.
BDIV0 BDIV1 DESCRIPTION
0 0 Divide by 16. Default power-on value. Recommended for
BCLK frequencies in the range of 8−60 MHz
0 1 Divide by 2. Recommended for BCLK frequencies in the range
of 1−11 MHz
1 0 Divide by 4. Recommended for BCLK frequencies in the range
of 2−22 MHz
1 1 Divide by 32. Recommended for BCLK frequencies in the
range of 16−80 MHz
18 DMACKCOMP Data-mover
acknowledge
complete
R/W Data-mover acknowledge complete. This bit controls the acknowledge response to
an asynchronous packet received and routed to the DM port. The default and
power-on value is 0, which causes the device to respond with an ack pending. A
value of 1 causes the device to respond with an ack complete for write request
packets.
19 FIFOACKCOMP FIFO
acknowledge
complete
R/W FIFO acknowledge complete. This bit controls the acknowledge response to an
asynchronous packet received and routed to the GRF. The default and power-on
value is 0, which causes the device to respond with an ack pending. A value of 1
causes the device to respond with an ack complete.
20 CYMAS Cycle master R/W When CYMAS is set and the TSB12LV32 is attached to the root Phy, the
cyclemaster function is enabled. When the cycle_count field of the cycle timer
register increments, the 1394 transmitter sends a cycle-start packet. When CYMAS
is cleared, the TSB12LV32 cannot be cyclemaster.
21 CYSRC Cycle source R/W When CYSRC is set, the cycle_count field increments and the cycle_offset field
resets for each positive transition of CYCLEIN. When CYSRC is cleared, the
cycle_count field increments when the cycle_offset field rolls over.
22 CYTEN Cycle timer
enable
R/W When CYTEN is set, the cycle_offset field increments.
23 CLSIDER Self-ID
error-code clear
W When CLSIDER is set, the SIDERCODE field (bits 24−27) is cleared. This bit clears
itself.
24−27 SID
ERROR
CODE
Self-ID error
code
R SID ERROR CODE contains the error code of the first self-ID error. The error code
is as follows:
0000 No error
0001 Last self-ID received was not all child ports
0010 Received Phy ID in self-ID not as expected
0011 Quadlet not inverted (phase error)
0100 Phy ID sequence error (two or more gaps in IDs)
0101 Phy ID sequence error (large gap in IDs)
0110 Phy ID error within packet
0111 Quadlet not the inverse of the prior quadlet
1000 Reserved
28 CMAUTO Auto set cycle
master
R/W When CMAUTO is high, the TSB12LV32 automatically enables CYMAS if this node
becomes the root following a bus reset.
29 IRP1EN IR port 1 enable R/W When IRP1EN is set, the 1394 receiver accepts isochronous packets when the
channel number matches the value in the IR port1 field at 18h.
30 IRP2EN IR port 2 enable R/W When IRP2EN is set, the 1394 receiver accepts isochronous packets when the
channel number matches the value in the IR Port2 field at 18h.
31 RESERVED Reserved