Datasheet

Internal Registers
10
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
2.2.3 Control Register at 08h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
RSTTX
RSTRX
CTNDRSTAT
CTNDRISIN
FLSHERR
RXSID
FULLSID
PHY_PKT_ENA
BSYCTRL
TXEN
RXEN
ENA_ACCEL
ENA_CONCAT
BUSNRST
BDIV0
BDIV1
DMACKCOMP
FIFOACKCOMP
CYMAS
CYSRC
CYTEN
CLSIDER
SID
CMAUTO
IRP1EN
IRP2EN
ENA_INSERT_IDLE
ERROR
CODE
The control register dictates the basic operation of the TSB12LV32. The power-up reset value of this register
equals E004 0200h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0 FLSHERR Flush GRF
on error
R/W This bit controls the flushing of the GRF when a packet with a data CRC error is
detected. The power-up value is 1, which means flush the GRF when a data CRC
error is detected.
1 RXSID Receive
self-ID packets
R/W If this bit is set, the self-identification (SID) packets generated by 1394 Phy devices
during the bus initialization phase are received and placed into the GRF as a single
packet. The default setting of this bit is 1. When this bit is set to 0, the SIDs are not
placed into the GRF. This bit must be set to 1 for the SELFIDEND interrupt to
function.
2 FULLSID Save full self-ID
packet
in GRF
R/W Save the full self-ID packets. When this bit is 1, the self-ID data quadlet and its
inverse quadlet are saved in the GRF. When this bit is 0, only the self-ID data
quadlet is saved in the GRF.
3 PHY_PKT_ENA Phy packets
receive enable
R/W Phy packet enable allows reception of all Phy packets. If this bit is set to 0, all Phy
packets, except for self-IDs, are rejected and interrupt HDERR (if not masked) is
generated. One HDERR interrupt is generated for every Phy packet received.
4 BSYCTRL Busy control R/W BSYCTRL controls which busy status the device returns to incoming packets.
When this bit is 0, the device follows normal busy/retry protocol: only send busy
when necessary. When this bit is 1, the device sends a busy acknowledge to all
incoming packets .
5 TXEN Transmit enable R/W When TXEN is cleared, the 1394 transmitter does not arbitrate or send packets.
TXEN bit is cleared following a bus reset, and all traffic through the DM port is
interrupted. TXEN must be set before packet transmit can resume. The power-on
reset value of TXEN is 0. If the TXEN bit is not set after a bus reset when the node is
master, the CYSTART terminal does not toggle.
6 RXEN Receive enable R/W When RXEN is cleared, the 1394 receiver does not receive any packets. This bit is
not affected by a bus reset and is set to 0 after a power-on reset.
7 ENA_ACCEL Acceleration
enable
R/W Enable acceleration. When this bit is set, fly-by acceleration and accelerated
arbitration are enabled. This bit cannot be set while TXEN and RXEN are set. This
bit can only be used with a 1394a-2000 capable Phy.
8 ENA_CONCAT Concatenation
enable
R/W Enable concatenation. When this bit is set it allows the link to concatenate multiple
isochronous or asynchronous packets. This bit can only be used with a 1394a-2000
capable Phy.
9 ENA_
INSERT_IDLE
Insert idle enable R/W Per the 1394a-2000 specification, the link is required to insert an idle state on the
control lines after the Phy grants the link control of the Phy/link interface. If using a
1394a-2000 Phy, this bit should be set to 1 in order for the link to drive an idle state
following the grant state from the Phy. For 1394-1995 Phys this bit must remain low.
10 RSTTX Transmitter reset R/W When RSTTX is set, the entire transmitter resets synchronously. This bit clears
itself.
11 RSTRX Receiver reset R/W When RSTRX is set, the entire receiver resets synchronously. This bit clears itself.
12 CTNDRSTAT Contender status R/W Contender status. On power up, this bit reflects the status of the CONTNDR pin.
When bit 13, CTNDRISIN, is 0 this bit is driven out to the CONTNDR pin. If
CTNDRISIN is 1 this bit is not used. (Only use on 1394-1995 Phys, or 1394a-2000
Phys when using hardware reset; otherwise, use the 1394a-2000 Phy registers to
set the node contender status).
13 CTNDRISIN Contender driver
enable
R/W Driver enable for the CONTNDR pin. On power up this bit is set to 1, which disables
the driver and allows reading of the state of the CONTNDR pin. Writing a 0 to this bit
enables the driver and drives bit 12, CTNDRSTAT, to output on the CONTNDR pin.
14 RESERVED Reserved