Datasheet

Internal Registers
9
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
BIT
NUMBER
DESCRIPTIONDIRFUNCTIONBIT NAME
13 BYTEMODE Byte mode R/W Byte mode. When this bit is set the DM port only looks at DM0−DM7. DM8−DM15 are
ignored for transmit and are not driven on receive. In this mode, the maximum speed
supported on the 1394 bus is 200 Mbps.
14 HANDSHK Handshake mode
(GPLynx mode)
R/W Handshake. When this bit is set, DMREADY and DMDONE are in strict handshake
mode (i.e., TSB12LV31 compatible mode). DMREADY must not be deactivated until
DMDONE activates. When DMDONE goes high, it checks for DMREADY low as an
acknowlegde. When this bit is set to 0, DMREADY may be deactivated before
DMDONE activates.
15 AUTOUP Automatic
address update
R/W Automatic update offset address. Valid only for asynchronous transmit using header
insert mode (bit 27, DMHDR, set to 0). For write request asynchronous packets,
header quadlet 2 contains the destination offset low address for the write. When this
bit is set, header quadlet 2 is updated by the value of the payload size (rounded up to
the nearest quadlet boundary).
16−20 DMACK DM
acknowledge
R DM acknowledge. This is the acknowledge received from the receiving node. This is
updated only when the transfer is from the DM port.
21 RESERVED Reserved
22−23 SPEED DM speed code R/W Speed code. This field is valid for isochronous transmit and asynchronous transmit
through the DM port. The DM logic uses this field to specify to the Phy the speed of
the data transfer.
24−25 CHNLCNT Channel count R/W Channel count. This field is valid only in isochronous transmit mode. This field allows
the node to transmit multiple data packets during a single isochronous period. The
device expects to transmit a packet on every active channel during each
isochronous cycle. If valid data is not provided, the value on the DM port is latched
and sent. Each packet must have a different channel number, however, hardware
does not check this. When the isochronous transmit header is supplied by the DM
interface or automatically inserted by the hardware, a maximum of four different
channels can be accessed in one isochronous period. In isochronous transmit with
automatic header insert, Header0−Header3 CFRs are used as the isochronous
header registers.
CHNLCNT = 00b, one channel / one packet per cycle
CHNLCNT = 01b, two channels / two packets per cycle
CHNLCNT = 10b, three channels / three packets per cycle
CHNLCNT = 11b, four channels / four packets per cycle
26 DMEN DM enable R/W DMEN controls the transmission of packets (asynchronous or isochronous) from the
DM port. If this bit is 0, transmission through from the DM port is inhibited. This bit is
typically used for asynchronous flow control. In normal operation, if an asynchronous
packet transmitted from the DM port receives an acknowledge from the receiving
node other than ack complete, this bit is set to 0 and DMERROR is asserted high.
Software must set this bit high to allow further transmission of asynchronous packets
from the DM port. The default and power-up value is 0.
27 DMHDR DM header
insert control
R/W DM header insert bit. When this bit is set to 0, the hardware automatically inserts the
header(s) into the DM transmit data. During receive, setting this bit to 0 strips off the
header(s)/trailer before routing packet to the DM. Header(s)/trailer are always
written to the CFR header/trailer registers regardless of the value of DMHDR.
28−29 AR0, AR1 Receive
control routing
R/W Receive packet routing control encoded bits. These bits in conjunction with
DMASYNC and DMRX, bits 30 and 31 in the DM control register, control the routing
of received packets to either the data-mover port or to the GRF. See Table 4−1.
30 DMASYNC DM
asynchronous
R/W If this bit is set to 1, the DM port is configured to transmit asynchronous traffic only. If
this bit is set to 0, the DM port is configured to transmit isochronous traffic only. The
DM port can not transmit both asynchronous and isochronous traffic simultaneously.
It must be configured for asynchronous (DMASYNC = 1) or isochronous (DMASYNC
= 0). The DM port can receive asynchronous and isochronous data packets
simultaneously. See Table 4−1 for more information.
31 DMRX DM receive R/W If this bit is set to 1, the DM port is configured to receive. If this bit is set to 0, the DM
port is configured to transmit. The DM port cannot both transmit and receive data at
the same time, it must be configured for either transmit or receive. See Table 4−1 for
more informaiton.