Datasheet
Internal Registers
8
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
Table 2−2. Header/Trailer Usage for CFRs 38h−48h
DIRECTION OF DM
DATA TRANSFER
PACKET TYPE
AUTO HEADER/
TRAILER INSERT/
EXTRACT
HEADER/TRAILER REGISTER
YES
Header0 CFR is formatted for isochronous transmission. Header1−header3
CFRs can be used for additional channels.
Data-Mover
TRANSMIT
Isochronous
NO
Isochronous header is supplied by the external device on the DM interface.
The header0 CFR is automatically written with the isochronous header ex-
tracted from the transmitted packet.
TRANSMIT
(to 1394 Bus)
Asynchronous/
YES Header0−header3 CFRs are formatted for asynchronous transmission.
Asynchronous/
asynchronous
stream packets
NO
Asynchronous header is supplied by the external device on the DM interface.
The header0−header3 CFRs are automatically written with the header ex-
tracted from the transmitted packet.
Isochronous/
asynchronous
YES
Header0−header3 CFRs and trailer CFR are automatically updated.
Isochronous headers are not streamed through the DM port. The trailer
quadlet is removed from the data stream.
Data-Mover
RECEIVE
asynchronous
stream packets
NO
Header0−header3 CFRs and trailer CFR are automatically updated. The iso-
chronous header is streamed through the DM port along with the payload
data. The trailer quadlet is appended to the data stream.
RECEIVE
(from 1394 Bus)
Asynchronous
YES
Header0−header3 CFRs and trailer CFR are automatically updated.
Asynchronous headers are not streamed through the DM port. The trailer
quadlet is removed from the data stream.
Asynchronous
NO
Header0−header3 CFRs and trailer CFR are automatically updated.
Asynchronous headers are streamed through the DM port along with data.
The trailer quadlet is appended to the data stream.
2.2 Configuration Register Definitions
2.2.1 Version Register at 00h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
01110001000101 010 011100 010100000
This register uniquely identifies this device to the software. The value is fixed at 7115 38A0h. This register is
read only.
2.2.2 Data-Mover Control Register at 04h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
PACKET PER BLOCK
ENDSWAP
HANDSHK
AUTOUP
DMACK
DMHDR
AR0
AR1
DMASYNC
DMRX
CHNLCNT
DMEN
SPEED
BYTEMODE
This register controls the data-mover port and must be set up before using the port. The power-up reset value
of this register equals 0000 0000h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0−11 PACKET
PER BLOCK
Data packets per
block transfer
R/W Number of data packets per block transfer. A block transfer is made up of multiple
data packets. A packet is the size of the data payload and is specified as part of the
header. This field remains fixed throughout the block transfer; it does not count down.
It does not change value until rewritten or reset. The data-mover logic uses this value
to activate DMDONE. In asynchronous mode, this field states how many packets the
DM should transfer before checking the status of DMREADY again. In isochronous
mode, this field states how many isochronous packets should be sent in the DM
cycle. These packets are sent over multiple channels if more than one isochronous
channel is active. The block transfer may take more than one isochronous cycle. This
field is only used in transmit mode.
12 ENDSWAP Endian swap R/W Swap endian. When this bit is set, the quadlet formed by stacking the DM data is byte
reversed, (i.e. the quadlet formed by fetching doublet AB01 then CD02 is
02CD 01AB instead of AB01 CD02).