Datasheet

Internal Registers
7
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
2 Internal Registers
2.1 TSB12LV32 Configuration Registers
Table 2−1. Configuration Register (CFR) Map
40h
38h
Header0
Asynchronous
Retry
Header1
Header3
Header2
NUMBER OF QUADLETS
ASYNC RETRY COUNT RETRY INTERVAL
ACKCODE SPD
Trailer
44h
3Ch
4Ch
48h
LPS_RESET
LPS_OFF
1Ch
20h
24h
28h−2Ch
B2_BUSY B3_BUSY
B0_PND
B1_PND B2_PND B3_PND
RAM_TEST
REGRW
RDPHY
ATFCLR
ATFFULL
GRFEMPTY
30h
34h
Diagnostic
Phy Access
Reserved
FIFO Status
Bus Reset
Maint_Control
PHYRGAD PHYRGDATA PHYRXAD PHYRXDATA
NRIDVAL
B0_BUSY B1_BUSY
STATSEL0 STATSEL1 STATSEL2
WRPHY
ATFWBMTY
GRFCLR
CD
ATACK GRFUSED
ROOT
CONTENDER
IRMNODEID BUS NUMBER NODE NUMBER
E_HCRC E_DCRC
NO_PKT
F_ACK
NO_ACK
0123456789101112131415161718192021222324252627 293031
00h
PHINT
SELFIDEND
ATSTARTED
SELFIDER
RXDMPKT
DM Control
Interrupt
Isochronous
Port
PHRRX
SNTRJ
CYDNE
CYSEC
CYST
CYLST
CARBFL
04h
0Ch
10h
14h
18h
28
IARBFL
ARBGP
SUBGP
HDRERR
08h
INT
ATFEMPTY
PHRST
Interrupt
Mask
Cycle Timer
VERSION
(711538A0h)
01110001000101010011100010100000
ENDSWAP
BYTEMODE
HANDSHK
AUTOUP
DMACK
DMHDR
AR0
AR1
DMASYNC
DMRX
CHNLCNT
DMEN
SPEED
RSTTX
RSTRX
CTNDRSTAT
CTNDRISIN
FLSHERR
RXSLD
FULLSID
PHY_PKT_ENA
BSYCTL
TXEN
RXEN
ENA_ACCEL
ENA_CONCAT
BUSNRST
BDIV0 BDIV1
DMACKCOMP
FIFOACKCOMP
CYMAS
CYSRC
CYTEN
CLSIDER
ERROR
SID
CODE
CMAUTO
IRP1EN IRP2EN
CMDRST
DMERROR
RXGRFPKT
ATSTK
TCERR
MCERROR
DMACKERR
FIFOACK
PHINT
SELFIDEND
ATSTARTED
SELFIDER
RXDMPKT
PHRRX
SNTRJ
CYDNE
CYSEC
CYST
CYLST
CARBFL
IARBFL
ARBGP
SUBGP
HDRERR
INT
ATFEMPTY
PHRST
CMDRST
DMERROR
RXGRFPKT
ATSTK
TCERR
MCERROR
DMACKERR
FIFOACK
SECONDS COUNT CYCLE COUNT
Control
TAG1 TAG2
MONTAG
ISYNCRCVN
IRCVALL
MSB LSB
LINKONLINKON
ENA_INSERT_IDLE
NOTES: A. All dark gray areas (bits) are reserved bits.
B. All light gray areas are read-only bits. All remaining are read/write bits.
PACKET PER BLOCK
IRPORT1
ATFAVAIL
NODECNT
IRPORT2
ACK
CYCLE OFFSET
PING VALUE
(See Section 2.2.13)
(See Section 2.2.14)
(See Section 2.2.15)
(See Section 2.2.16)