Datasheet

Overview
6
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
1.5.1 STAT0, STAT1, and STAT2 Programming
The STAT0, STAT1, and STAT2 terminals can be independently programmed to show one of 14 possible
internal hardware status signals. The controls for the STAT terminals are in the Diagnostic register at address
20h of the CFR register. STAT0 is controlled by STATSEL0 (bits 16-19), STAT1 is controlled by bits STATSEL1
(bits 20−23), and STAT2 is controlled by STATSEL2 (bits 24−27). See Table 1−2 for programming the STAT
terminals.
Table 1−2. STAT Terminal Programming
STATSEL0, STATSEL1,
OR STATSEL2
STAT0/STAT1/STAT2 DESCRIPTION
0 0 0 0 Reserved Reserved
0 0 0 1 ATFFULL Indicates that the ATF is full. Bit 12 in the FIFO status CFR at 30h.
0 0 1 0 Bus reset (PHYRST) 1394 bus reset. Bit 3 in the Interrupt CFR at 0Ch.
0 0 1 1 Arbitration reset gap
The 1394 bus has been idle for an arbitration reset gap. Bit 26 in the interrupt CFR
at 0Ch.
0 1 0 0 CYCLEOUT
Cycle out. The LLC clock. It is based on the timer controls and the received
cycle-start messages.
0 1 0 1 RXDMPKT
Packet received to DM interrupt. Activated at the end of a received packet. Bit 9 in
the interrupt CFR at 0Ch.
0 1 1 0 RXGRFPKT
Packet received to GRF interrupt. Activated at the end of a received packet. Bit 6 in
the interrupt CFR at 0Ch.
0 1 1 1 BX_BUSY Byte busy. This represents the OR of bits 0−3 of the diagnostic CFR at 20h.
1 0 0 0 SUBGP
Subaction gap. Activated upon detection of a subaction gap. Bit 27 in the interrupt
CFR at 0Ch.
1 0 0 1 CYCLE_DONE
Cycle done. Indicates the end of the isochronous period. This happens when a
subaction gap has been detected. Bit 22 in the interrupt CFR at 0Ch.
1 0 1 0
ATSTARTED
(default setting for STAT1)
Activated when an asynchronous packet transfer has started from the ATF. Bit 5 in
the interrupt CFR at 0Ch.
1 0 1 1 DMACKERR DM acknowledge was not complete. Bit 17 in the interrupt CFR at 0Ch.
1 1 0 0 DMEN DM enable. Bit 26 in the DM control CFR at 04h.
1 1 0 1
GRFEMPTY
(default setting for STAT2)
GRF is empty. Bit 15 in the FIFO status CFR at 30h.
1 1 1 0 Reserved Reserved
1 1 1 1 Reserved Reserved
NOTE: An interrupt remains set until cleared by writing a 1 to the interrupt CFR at 0CH, but the associated STAT signal pulses for only one clock
cycle.
1.6 Ordering Information
TEMPERATURE ORDERING NUMBER
TOP-SIDE MARKING
PACKAGE
−40°C to 110°C
TSB12LV32TPZEP TSB12LV32TEP 100-Terminal PQFP