Datasheet
Overview
5
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
Table 1−1. Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
Data-Mover Port Interface (Continued)
DMRW 49 O Data-mover read/write indicator. When data is being moved from 1394 to the DM port (receive) this signal
goes high to indicate data is available on DMD[0:15]. When data is being moved from DM to 1394 bus
(transmit) this signal goes high to indicate that data must be supplied to the DMD[0:15] port for
transmission.
PKTFLAG 51 O Packet flag. PKTFLAG is asserted high to indicate the first (header) or last (trailer) quadlet of a received
packet on the DM interface. PKTFLAG is not valid in transmit mode. The PKTFLAG signal is not valid
when the header/trailer extraction option is selected.
Phy/Link Interface
CTL[0:1] 70, 69 I/O Phy-link interface control lines
D[0:7] 67, 66,
63−58
I/O Phy-link interface data lines. Data is only expected on D0 and D1 at 100 Mbps, D0−D3 at 200 Mbps, and
D0−D7 at 400 Mbps. D0 is the MSB bit.
LINKON 64 I Link-on from the Phy is a 4 MHz − 8 MHz clock. This signal is activated when the link is inactive and the
Phy has detected a link-on packet or a Phy interrupt. This clock persists for no more than 500 ns. When
the link detects this terminal as active, it turns on and drives LPS.
LPS 53 O Link power status. LPS is used to drive the LPS input of the Phy. It indicates to the Phy that the link is
powered up and active. LPS toggles at a rate = 1/16 of BCLK by default (see CFR at 08h for more
information).
LREQ 74 O Link request to Phy. LREQ makes bus requests and register access requests to the Phy.
SCLK 72 I System clock. SCLK is a 49.152-MHz clock supplied by the Phy. DMCLK is generated from SCLK. SCLK
can also be used as the source for BCLK.
Miscellaneous Functions
CONTNDR 65 I/O Contender. When asserted high, this terminal tells the link that this node is a contender for isochronous
resource manager (IRM) or bus manager functions. The state of CONTNDR must match the state of the
Phy contender terminal for 1394-1995 compliant Phys, and the Phy register bit for 1394a−2000 compliant
Phys. This terminal defaults to being an input on power up. After power up, the value of this terminal can
be driven internally by the CTNDRSTAT bit (bit 12 at 08h). Additional CSRs must be implemented in
software for the device to support IRM functionality.
CYCLEIN 76 I Cycle in. This input is an optional external 8-kHz clock used as the isochronous cycle clock. It only is used
if attached to the cycle-master node. It is enabled by the cycle source bit and should be tied high when not
used.
CYSTART 2 O Isochronous cycle start indicator. CYSTART signals the beginning of an isochronous cycle by pulsing for
one DMCLK period.
DIRECT 79 I Isolation terminal. When this terminal is asserted high, no isolation is present between the TSB12LV32
and the Phy. When low, the Texas Instruments bus holder isolation is active.
GND 5, 25, 30,
45, 57, 73,
78, 90,
100
Ground reference
INT 1 O Interrupt. NOR of all internal interrupts.
9 I
STAT[0:2] 54−56 O General status outputs. STATn is the output signal selected with the CFR at address 20h.
TESTMODE 16 I This terminal is used to place the TSB12LV32 in the test mode (for Texas Instruments internal use only).
In normal operation, this terminal must be tied to ground.
V
DD
5V 10, 35, 85 5 V (± 0.5 V) supply voltage for 5-V tolerant inputs. Only the Phy/link interface of the TSB12LV32 is not
5-V tolerant. Tie this terminal to the 3.3-V supply voltage if the TSB12LV32 is not connected to any
devices driving 5-V signals. Tie this terminal to the 5-V supply voltage if the TSB12LV32 is connected to
any devices driving 5-V signals. This terminal is only used to make inputs 5-V tolerant, it is not used for
any outputs.
V
DD
15, 20, 40,
47, 68, 71,
80, 95
3.3 V (±0.3 V) supply voltage