Datasheet

Overview
4
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
1.5 Terminal Functions
The terminal functions are described in Table 1−1. No input terminals or I/O terminals should be left floating;
unless otherwise specified, connect any unused input terminals or I/O terminals to ground using 1-kΩ
resistors.
Table 1−1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
Microcontroller/Microprocessor Interface
BCLK 6 I Microcontroller interface clock. Maximum frequency is 60 MHz. In the ColdFire mode, BCLK is the same as
CLK, which is the clock-input signal to the ColdFire.
COLDFIRE 12 I ColdFire mode. To operate in this mode, COLDFIRE must be asserted high.
LENDIAN 75 I Little-endian mode for the microcontroller interface. When this terminal is pulled up, the data on MD0−MD15
is byte-swapped to little endian byte format before it is written to the CFR or FIFO and after it is read from the
CFR or FIFO.
MA[0:6] 24−21
19−17
I Microcontroller address bus. MA0 is the most significant bit (MSB) of these 7 bits.
M8BIT/SIZ0 13 I Configuration bit for microcontroller interface. If the microcontroller interface is 8 bits wide, this terminal must
be pulled up to the supply voltage. In ColdFire mode, this terminal represents burst SIZ0.
MCMODE/SIZ1 14 I Mode bit for microcontroller interface. If the microcontroller interface is used in a handshake mode, this
terminal must be pulled up to the supply voltage. In ColdFire mode, this terminal represents burst SIZ1.
MCA 4 O Microcontroller interface cycle acknowledge. When asserted low, MCA signals an acknowledge of the
microcontroller cycle from the TSB12LV32.
MCS 7 I Microcontroller interface cycle start. When asserted low, MCS signals the beginning of a microcontroller
operation to the TSB12LV32.
MDINV 11 I Microcontroller interface data invariant mode. This terminal is meaningful only when LENDIAN (75) is high.
When asserted high, the microcontroller interface operates in the data invariant mode. When low, the
microcontroller interface operates in address invariant mode.
MD[0:15] 99−96
94−91
89−86
84−81
I/O Microcontroller interface bidirectional data bus. MD0 is the most significant bit. However, byte significance is
dependent on the state of the LENDIAN and MDINV terminals.
MWR 8 I Microcontroller read/write indicator. When driven high, MWR indicates a read access from the TSB12LV32.
When driven low, MWR
indicates a write access to the TSB12LV32.
TEA 3 O Transfer error acknowledge. This active-low signal is asserted low for one BCLK cycle whenever there is an
illegal transfer request by the microcontroller (i.e., requested data transfer size is unsupported or MCS
is
asserted low for more than one BCLK cycle in ColdFire mode).
Data-Mover Port Interface
DMD[0:15] 26–29
31–34
36–39
41–44
I/O Data-mover (DM) bidirectional data port. DMD0 is the MSB of these 16 bits.
DMCLK 46 O Data-mover clock at (SCLK/2) MHz
DMDONE 50 O Data mover done. For transmit, this signal is activated when the internal packet counter counts down to zero
from the value loaded into the PACKET PER BLOCK field in the CFR @ 04h. For receive, this terminal pulses
for one DMCLK prior to the first byte/word available to the DM interface.
DMERROR 52 O Data-mover error. DMERROR is asserted high when there is an error in the received packet or an illegal
transmit speed was attempted.
DMPRE 48 O Data-mover predata indicator. In transmit mode, DMPRE pulses for one DMCLK prior to accepting the first
quadlet on the DM port. In isochronous receive mode, DMPRE pulses for one DMCLK when the sync bit in the
header matches a bit set in the isochronous port CFR at 18h. DMPRE is not used in asynchronous receive
mode.
DMREADY 77 I Data mover ready. Must be asserted high by the external logic controlling the DM interface when data is ready
for transmit. DMREADY must be set low when the data mover is in receive mode. DMREADY cannot be used
to throttle the data rate through the data-mover port; see Section 5 for more information.