Datasheet

12
The following are features of the TSB12LV01B.
1.1.1 Link Core
Supports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus
Transmits and Receives Correctly Formatted 1394 Packets
Supports Asynchronous and Isochronous Data Transfers
Performs Function of 1394 Cycle Master
Generates and Checks 32-Bit CRC
Detects Lost Cycle-Start Messages
Contains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K Bytes
1.1.2 Physical-Link Interface
Compatible With Texas Instruments Physical Layer Devices (PHYs)
Supports Transfer Speeds of 100, 200, and 400 Mbits/s
Timing Compliant with IEEE 1394a2000
1.1.3 Host Bus Interface
Provides Chip Control With Directly Addressable Registers
Is Interrupt Driven to Minimize Host Polling
Has a Generic 32-Bit Host Bus Interface
1.1.4 General
Operates From a 3.3-V Power Supply While Maintaining 5-V Tolerant Inputs
Manufactured With Low-Power CMOS Technology
100-Pin PZT Package for -40°C to 85°C (I Temperature) Operation
1.1.5 Enhanced Plastic
Controlled Baseline
One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of 40°C to 85°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such
qualification testing should not be viewed as justifying use of this component beyond specified performance and
environmental limits.
1.1.6 Ordering Information
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40°C to 85°C PQFP PZT TSB12LV01BIPZTEP 12LV01BIEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.