Datasheet

7–9
After sending the last packet for the current bus ownership, the TSB12LV01B releases the bus by asserting
idle on the CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock
cycle after sampling idle from the link. Note, that whenever the D and CTL terminals change direction
between the PHY and the TSB12LV01B, there is an extra clock period allowed so that both sides of the
interface can operate on registered versions of the interface signals.
00
00 00001001
000000
000011
dnd0
SYSCLK
CTL0, CTL1
D0–D7
01
00
SPD
00
(a) (b) (c) (d) (e) (g)
(f)
Link Controls CTL and D
PHY CTL and D Outputs Are High
Impedance
NOTE: SPD = Speed code, see Table 7–11. d0–dn = Packet data
Figure 7–6. Normal Packet Transmission Timing
The sequence of events for a normal packet transmission is as follows:
• Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over
control of the interface to the link so that the link may transmit a packet. The PHY releases control
of the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle
cycle.
• Optional idle cycle. The link may assert, at most, one Idle cycle preceding assertion of either hold
or transmit. This idle cycle is optional; the link is not required to assert Idle preceding either hold
or transmit.
• Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit.
These hold cycle(s) are optional; the link is not required to assert hold preceding transmit.