Datasheet

7–8
The sequence of events for a null packet reception is as follows:
• Receive operation initiated. The PHY indicates a receive operation by asserting receive on the
CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation
may interrupt a status transfer operation that is in progress so that the CTL lines may change from
status to receive without an intervening idle.
• Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more
cycles.
• Receive operation terminated. The PHY terminates the receive operation by asserting idle on the
CTL lines. The PHY shall assert at least one cycle of idle following a receive operation.
Table 7–11. Receive Speed Codes
D0 – D7 DATA RATE
00XXXXXX
†
S100
0100XXXX
†
S200
01010000 S400
1YYYYYYY
‡
Data-on indication
†
X = output as 0 by PHY, ignored by
TSB12LV01B.
‡
Y = output as 1 by PHY, ignored by
TSB12LV01B.
7.5 Transmit Operation
When the TSB12LV01B issues a bus request through the LREQ terminal, the PHY arbitrates to gain control
of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the
TSB12LV01B by asserting the grant state (’b11) on the CTL terminals for one SYSCLK cycle, followed by
idle for one clock cycle. The TSB12LV01B then takes control of the bus by asserting either idle (’b00), hold
(’b01) or transmit (’b10) on the CTL terminals. Unless the TSB12LV01B is immediately releasing the
interface, the TSB12LV01B may assert the idle state for at most one clock cycle before it must assert either
hold or transmit on the CTL terminals. The hold state is used by the TSB12LV01B to retain control of the
bus while it prepares data for transmission. The TSB12LV01B may assert hold for zero or more clock cycles
(i.e., the TSB12LV01B need not assert hold before transmit). The PHY asserts data-prefix on the serial bus
during this time.
When the TSB12LV01B is ready to send data, the TSB12LV01B asserts transmit on the CTL terminals as
well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals
until the last bits of data has been sent. The TSB12LV01B then asserts either hold or idle on the CTL
terminals for one clock cycle, and then asserts Idle for one additional cycle before releasing the interface
bus and placing its CTL and D terminals in high-impedance. The PHY then regains control of the interface
bus.
The hold state asserted at the end of packet transmission indicates to the PHY that the TSB12LV01B
requests to send another packet (concatenated packet) without releasing the serial bus. The PHY responds
to this concatenation request by waiting the required minimum packet separation time and then asserting
grant, as before. This function may be used to send a unified response after sending an acknowledge, or
to send consecutive isochronous packets during a single isochronous period. Unless multispeed
concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed
(since the speed of the packet is set before the first packet). If multispeed concatenation is enabled (when
the EMSC bit of PHY register 5 is set), the TSB12LV01B must specify the speed code of the next
concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet.
The encoding for this speed code is the same as the speed code that precedes received packet data as
given in Table 7–11.