Datasheet

7–7

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus

followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet

speed exceeds the capability of the receiving PHY, or whenever the TSB12LV01B immediately releases the

bus without transmitting any data. In this case, the PHY will assert receive on the CTL terminals with the

data-on indication (all 1’s) on the D terminals, followed by idle on the CTL terminals, without any speed code

or data being transferred. In all cases, the TSB41LV03B sends at least one data-on indication before

sending the speed code or terminating the receive operation.

The TSB41LV03B also transfers its own self-ID packet, transmitted during the self-ID phase of bus

initialization, to the TSB12LV01B. This packet is transferred to the TSB12LV01B just as any other received

self-ID packet.

0010

XX dnd0

(a)

(e)(d)(b) (c)

FF (Data-on)

SPD

SYSCLK

CTL0, CTL1

D0–D7

Figure 7–4. Normal Packet Reception Timing

The sequence of events for a normal packet reception is as follows:

• Receive operation initiated. The PHY indicates a receive operation by asserting receive on the

CTL lines. Normally, the interface is Idle when receive is asserted. However, the receive

operation may interrupt a status transfer operation that is in progress so that the CTL lines may

change from status to receive without an intervening idle.

• Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more

cycles preceding the speed-code.

• Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on

the D lines for one cycle immediately preceding the packet data. The link decodes the

speed-code on the first receive cycle for which the D lines are not the data-on code. If the

speed-code is invalid, or indicates a speed higher than that which the link is capable of handling,

the link should ignore the subsequent data.

• Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts

packet data on the D lines with receive on the CTL lines for the remainder of the receive operation.

• Receive operation terminated. The PHY terminates the receive operation by asserting idle on the

CTL lines. The PHY asserts at least one cycle of idle following a receive operation.

0010

(a)

(b) (c)

SYSCLK

CTL0, CTL1

D0–D7

FF (Data-on)

Figure 7–5. Null Packet Reception Timing