Datasheet

7–6
Table 7–10. Status Bits
BIT(s) NAME DESCRIPTION
0 Arbitration reset
gap
Indicates that the PHY has detected that the bus has been idle for an arbitration reset
gap time (as defined in IEEE Std 1394-1995). This bit is used by the TSB12LV01B in
the busy/retry state machine.
1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time
(as defined in IEEE Std 1394-1995). This bit is used by the TSB12LV01B to detect the
completion of an isochronous cycle.
2 Bus reset Indicates that the PHY has entered the bus reset start state.
3 Interrupt Indicates that a PHY interrupt event has occurred. An interrupt event may be a
configuration time-out, cable-power voltage falling too low, a state time-out, or a port
status change.
4–7 Address This field holds the address of the PHY register whose contents are being transferred
to the TSB12LV01B.
8–15 Data This field holds the register contents.
00
00
(a)
01
(b)
00
00
SYSCLK
CTL0, CTL1
D0, D1
S[0:1] S[14:15]
Figure 7–3. Status Transfer Timing
The sequence of events for a status transfer is as follows:
• Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines
along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status transfer will be either 2 or 8 cycles
long. A 2-cycle (4-bit) transfer occurs when only status information is to be sent. An 8-cycle
(16-bit) transfer occurs when register data is to be sent in addition to any status information.
• Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on
the CTL lines. The PHY may also interrupt a status transfer at any cycle by asserting receive on
the CTL lines to begin a receive operation. The PHY shall assert at least one cycle of idle between
consecutive status transfers.
7.4 Receive Operation
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates
the start of a packet by placing the speed code (encoded as shown in Table 7–11 on the D terminals, followed
by the packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet
has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All
received packets are transferred to the TSB12LV01B. Note that the speed code is part of the PHY-LLC
protocol and is not included in the calculation of CRC or any other data protection mechanisms.