Datasheet
7–5
For write register requests, the PHY loads the specified data into the addressed register as soon as the
request transfer is complete. For read register requests, the PHY returns the contents of the addressed
register to the TSB12LV01B at the next opportunity through a status transfer. If a received packet interrupts
the status transfer, then the PHY continues to attempt the transfer of the requested register until it is
successful. A write or read register request may be made at any time, including while a bus request is
pending. Once a read register request is made, the PHY ignores further read register requests until the
register contents are successfully transferred to the TSB12LV01B. A bus reset does not clear a pending read
register request.
The TSB41LV03A includes several arbitration acceleration enhancements, which allow the PHY to improve
bus performance and throughput by reducing the number and length of inter-packet gaps. These
enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and
priority packet concatenation onto acknowledge packets, and accelerated fair and priority request
arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY
register 5 is set.
The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit
the cycle start message under certain circumstances. The acceleration control request is therefore provided
to allow the TSB12LV01B to temporarily enable or disable the arbitration acceleration enhancements of the
TSB41LV03A during the asynchronous period. The TSB12LV01B typically disables the enhancements
when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then
re-enables the enhancements when it receives a cycle start message. The acceleration control request may
be made at any time and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus
request will cause the enhancements to be re-enabled, if the EAA bit is set.
7.3 Status Transfer
A status transfer is initiated by the PHY when there is status information to be transferred to the
TSB12LV01B. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated
by the PHY asserting status (‘b01) on the CTL terminals, along with the first two bits of status information
on the D[0:1] terminals. The PHY maintains CTL = status for the duration of the status transfer. The PHY
may prematurely end a status transfer by asserting something other than status on the CTL terminals. This
occurs if a packet is received before the status transfer completes. The PHY continues to attempt to
complete the transfer until all status information has been successfully transmitted. There is at least one idle
cycle between consecutive status transfers.
The PHY normally sends just the first four bits of status to the TSB12LV01B. These bits are status flags that
are needed by the TSB12LV01B state machines. The PHY sends an entire 16-bit status packet to the
TSB12LV01B after a read register request, or when the PHY has pertinent information to send to the
TSB12LV01B or transaction layers. The only defined condition where the PHY automatically sends a
register to the TSB12LV01B is after self-ID, where the PHY sends the physical-ID register that contains the
new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The
status flags are considered to have been successfully transmitted to the TSB12LV01B immediately upon
being sent, even if a received packet subsequently interrupts the status transfer Register contents are
considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status
transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer
has not yet completed.
The definitions of the bits in the status transfer are shown in Table 7–10 and the timing is shown in
Figure 7–3.