Datasheet

7–4
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 7–7.
Table 7–7. Read Register Request
BIT(S) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–3 Request type A 100 indicates this is a read register request.
4–7 Address Identifies the address of the PHY register to be read
8 Stop bit Indicates the end of the transfer (always 0)
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 7–8.
Table 7–8. Write Register Request
BIT(S) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–3 Request type A 101 indicates this is a write register request.
4–7 Address Identifies the address of the PHY register to be written to
8–15 Data Gives the data that is to be written to the specified register address
16 Stop bit Indicates the end of the transfer (always 0)
For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 7–9.
Table 7–9. Acceleration Control Request
BIT(S) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–3 Request type A 110 indicates this is an acceleration control request.
4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0
5 Stop bit Indicates the end of the transfer (always 0)
For fair or priority access, the TSB12LV01B sends the bus request (FairReq or PriReq) at least one clock
after the PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (’b10) by
the PHY, then any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or
priority requests if the receive state is asserted while the TSB12LV01B is sending the request. The
TSB12LV01B may then reissue the request one clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving
or transmitting a cycle start message, the TSB12LV01B can issue an isochronous bus request (IsoReq).
The PHY will clear an isochronous request only when the serial bus has been won.
To send an acknowledge packet, the TSB12LV01B must issue an immediate bus request (ImmReq) during
the reception of the packet addressed to it. This is required in order to minimize the idle gap between the
end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive
packet ends, the PHY immediately grants control of the bus to the TSB12LV01B. The TSB12LV01B sends
an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case,
the TSB12LV01B does not transmit an acknowledge, but instead cancels the transmit operation and
releases the interface immediately; the TSB12LV01B must not use this grant to send another type of packet.
After the interface is released the TSB12LV01B may proceed with another request.
The TSB12LV01B may make only one bus request at a time. Once the TSB12LV01B issues any request
for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY
indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus
arbitration won and the TSB12LV01B granted control). The PHY ignores new bus requests while a previous
bus request is pending. All bus requests are cleared upon a bus reset.