Datasheet

7–2
The ISO terminal is used to enable the output differentiation logic on the CTL0-CTL1 and D0-D7 terminals.
Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY
and TSB12LV01B.
The TSB41LV03A normally controls the CTL0–CTL1 and D0-D7 bidirectional buses. The TSB12LV01B is
allowed to drive these buses only after the TSB12LV01B has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer,
data transmit, and data receive. The TSB12LV01B issues a service request to read or write a PHY register,
to request the PHY to gain control of the serial-bus in order to transmit a packet, or to control arbitration
acceleration.
The PHY may initiate a status transfer either autonomously or in response to a register read request from
the TSB12LV01B. The PHY initiates a receive operation whenever a packet is received from the serial-bus.
The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the
TSB12LV01B. The transmit operation is initiated when the PHY grants control of the interface to the
TSB12LV01B.
The encoding of the CTL0–CTL1 bus is shown in Table 7–1 and Table 7–2.
Table 7–1. CTL Encoding When the PHY Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION OF ACTIVITY
0 0 Idle No activity (this is the default mode).
0 1 Status Status information is being sent from the PHY layer to the TSB12LV01B.
1 0 Receive An incoming packet is being sent from the PHY layer to the TSB12LV01B.
1 1 Grant The TSB12LV01B is given control of the bus to send an outgoing packet.
Table 7–2. CTL Encoding When the TSB12LV01B Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION OF ACTIVITY
0 0 Idle The TSB12LV01B releases the bus (transmission has been completed).
0 1 Hold The TSB12LV01B is holding the bus while data is being prepared for transmission, or
indicating that another packet is to be transmitted (concatenated) without arbitrating.
1 0 Transmit An outgoing packet is being sent from the TSB12LV01B to the PHY.
1 1 Reserved None
7.2 TSB12LV01B Service Request
To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the
TSB12LV01B sends a serial bit stream on the LREQ terminal as shown in Figure 7–2.
LR2 LR3LR1LR0 LR(n-1)
LR
(n-2)
Figure 7–2. LREQ Request Stream
The length of the stream will vary depending on the type of request as shown in Table 7–3.
Table 7–3. Request Stream Bit Length
NAME NUMBER of BITS
Bus request 7 or 8
Read register request 9
Write register request 17
Acceleration control request 6