Datasheet

7–1
7 TSB12LV01B to 1394 PHY Interface Specification
This chapter provides an overview of the digital interface between a TSB12LV01B and a physical layer
device (PHY). The information that follows can be used as a guide through the process of connecting the
TSB12LV01B to a 1394 PHY. The part numbers referenced, the TSB41LV03A and the TSB12LV01B,
represent the Texas Instruments implementation of the PHY (TSB41LV03A) and link (TSB12LV01B) layers
of the IEEE 1394-1995 and P1394a standards.
The specific details of how the TSB41LV03A device operates are not discussed in this document. Only those
parts that relate to the TSB12LV01B PHY interface are mentioned.
7.1 Principles of Operation
The TSB12LV01B is designed to operate with a Texas Instruments physical-layer device. The following
paragraphs describe the operation of the PHY-LLC interface assuming a TSB41LV03A PHY. The
TSB41LV03A is an IEEE 1394a three port cable transceiver/arbiter PHY capable of 400 Mbits/s speeds.
The interface to the PHY consists of the SCLK, CTL0–CTL1, D0–D7, LREQ, and POWERON terminals on
the TSB12LV01B, as shown in Figure 7–1.
ISO
D0 – D7
CTL0 – CTL1
LREQ
SCLK
Link Layer
Controller
Physical-Layer
Device
TSB12LV01B TSB41LV03A
CTL0 – CTL1
SYSCLK
LREQ
D0 – D7
LPSPOWERON
PHY/LLC Interface
ISO
Figure 7–1. PHY-LLC Interface
The SYSCLK from the PHY terminal provides a 49.152-MHz interface clock. All control and data signals are
synchronized to, and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and
data between the TSB41LV03A and TSB12LV01B.
The D0-D7 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB41LV03A supports S100, S200, and S400 data
transfers over the D0-D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200
operation only the D0-D3 terminals are used; and in S400 operation all D0-D7 terminals are used for data
transfer. When the TSB41LV03A is in control of the D0-D7 bus, unused Dn terminals are driven low during
S100 and S200 operations. When the TSB12LV01B is in control of the D0-D7 bus, unused Dn terminals
are ignored by the TSB41LV03A.
The LREQ terminal is controlled by the TSB12LV01B to send serial service requests to the PHY in order
to request access to the serial-bus for packet transmission, read or write PHY registers, or control arbitration
acceleration.
The POWERON and LPS terminals are used for power management of the PHY and TSB12LV01B. The
POWERON terminal indicates the power status of the TSB12LV01B, and may be used to reset the PHY-LLC
interface or to disable SYSCLK.