Datasheet

6–4
BCLK
(Input)
(
see Note A)
DATA0 –
DATA31
(Output)
ADDR0 –
ADDR7
(Input)
CA
(Output)
(
see Note B)
WR
(Input)
CS
(Input)
DATA8DATA1 DATA2 DATA7 DATA9
1028910
t
d1
t
d4
t
d3
t
d2
NOTES: A. At the (nth+1) BCLK rising edge, host bus should latch DATAn.
B. CA
is one cycle delay from respective CS.
C. These waveforms only apply to address C0h.
Figure 6–7. Burst Read Waveforms
t
w2(L)
50% 50%
SCLK
(Input)
t
w2(H)
50%
t
c2
Figure 6–8. SCLK Waveform
t
d8
t
d6
t
d10
50% 50% 50%
SCLK
(Input)
D0 – D7
(Output
)
CTL0 – CTL1
(Output)
t
d7
t
d5
t
d9
Figure 6–9. TSB12LV01B-to-PHY-Layer Interface Transfer Waveforms