Datasheet

6–3
BCLK
(Input)
DATA0 –
DATA31
(Output)
ADDR0 –
ADDR7
(Input)
CA
(Output)
WR
(Input)
CS
(Input)
ADDR1 ADDR2
DATA1 DATA2
t
d2
t
d3
t
d4
t
d1
NOTE A. There must be a minimum of 3 rising edges of BCLK between assertions of CS.
Figure 6–5. Host-Interface Quick Read-Cycle Waveforms (ADDRESS ≥ 30h)
BCLK
(Input)
(see Note A)
DATA0 –
DATA31
(Input)
ADDR0 –
ADDR7
(Input)
CA
(Output)
(
see Note B)
WR
(Input)
CS
(Input)
DATA1 DATA2 DATA3 DATA8 DATA9
1028910
t
d2
t
h1
t
su1
t
d1
NOTES: A. At the nth BCLK rising edge, DATAn is written into the FIFO.
B. CA
is one cycle delay from respective CS.
Figure 6–6. Burst Write Waveforms