Datasheet

6–2
BCLK
(Input)
DATA0 –
DATA31
(Output)
ADDR0 –
ADDR7
(Input)
CA
(Output)
WR
(Input)
CS
(Input)
t
su2
t
d3
t
su4
t
d2
t
su3
t
d1
t
d4
t
h3
t
h4
t
h2
NOTE A. Following a CS assertion, there may be a maximum of 9 rising edges of BCLK before a CA is returned. CA
must be returned before another CS may be asserted.
Figure 6–3. Host-Interface Read-Cycle Waveforms (Address: 00h – 2Ch)
BCLK
(Input)
DATA0 – DATA31
(Input)
ADDR0 – ADDR7
(Input)
CA
(Output)
WR
(Input)
CS
(Input)
ADDR2
DATA2
t
su2
t
su4
t
su3
t
h4
t
d2
t
su1
t
h1
t
h2
t
h3
t
d1
ADDR1
DATA1
NOTE A. There must be a minimum of 3 rising edges of BCLK between assertions of CS.
Figure 6–4. Host-Interface Quick Write-Cycle Waveforms (Address ≥ 30h)