Datasheet

6–1
6 Parameter Measurement Information
t
w1(L)
50% 50%
BCLK
(Input)
t
w1(H)
50%
t
c1
Figure 6–1. BCLK Waveform
DATA0 – DATA31
(Input)
ADDR0 – ADDR7
(Input)
CA
(Output)
WR
(Input)
CS
(Input)
t
su1
t
h1
t
h2
t
su2
t
su3
t
su4
t
h3
t
d1
t
d2
t
h4
BCLK
(Input)
NOTE A. Following a CS assertion, there may be a maximum of 9 rising edges of BCLK before a CA is returned. CA
must be returned before another CS may be asserted.
Figure 6–2. Host-Interface Write-Cycle Waveforms (Address: 00h – 2Ch)