Datasheet

53
5.4 Host-Interface Timing Requirements, T
A
= 25°C (see Note 3)
PARAMETER MIN MAX UNIT
t
c1
Cycle time, BCLK (see Figure 61) 20 111 ns
t
w1(H)
Pulse duration, BCLK high (see Figure 61) 8.6 ns
t
w1(L)
Pulse duration, BCLK low (see Figure 61) 8.6 ns
t
su1
Setup time, DATA0 DATA31 valid before BCLK (see Figures 62, 64, 66) 4 ns
t
h1
Hold time, DATA0 DATA31 valid after BCLK (see Figures 62, 64, 66) 2 ns
t
su2
Setup time, ADDR0ADDR7 valid before BCLK (see Figures 62, 63, 64) 8 ns
t
h2
Hold time, ADDR0 ADDR7 valid after BCLK (see Figures 62, 63, 64) 2 ns
t
su3
Setup time, CS low before BCLK (see Figures 62, 63, 64) 8 ns
t
h3
Hold time, CS low after BCLK (see Figures 62, 63, 64) 2 ns
t
su4
Setup time, WR valid before BCLK (see Figures 62, 63, 64) 8 ns
t
h4
Hold time, WR valid after BCLK (see Figures 62, 63, 64) 2 ns
NOTE 3: These parameters are not production tested.
5.5 Host-Interface Switching Characteristics Over Recommended Operating
Free-Air Temperature Range, C
L
= 45 pF (Unless Otherwise Noted)
PARAMETER MIN MAX UNIT
t
d1
Delay time, BCLK to CA(see Figures 62, 63, 65, 66, 67) 2.5 8 ns
t
d2
Delay time, BCLK to CA (see Figures 62, 63, 65, 66, 67) 2.5 8 ns
t
d3
Delay time, BCLK to DATA0 DATA31 valid (see Figures 63, 65, 67, and
Note 3)
2.5 10 ns
t
d4
Delay time, BCLK to DATA0 DATA31 invalid (see Figures 63, 65, 67, and
Note 3)
2.5 10 ns
NOTE 3: These parameters are not production tested.
5.6 Cable PHY-Layer-Interface Timing Requirements Over Recommended
Operating Free-Air Temperature Range (see Note 3)
PARAMETER MIN MAX UNIT
t
c2
Cycle time, SCLK (see Figure 68) 20.347 20.343 ns
t
w2(H)
Pulse duration, SCLK high (see Figure 68) 9 ns
t
w2(L)
Pulse duration, SCLK low (see Figure 68) 9 ns
t
su5
Setup time, D0 D7 valid before SCLK (see Figure 610) 4 ns
t
h5
Hold time, D0 D7 valid after SCLK (see Figure 610) 0 ns
t
su6
Setup time, CTL0 CTL1 valid before SCLK (see Figure 610) 4 ns
t
h6
Hold time, CTL0 CTL1 valid after SCLK (see Figure 610) 0 ns
NOTE 3: These parameters are not production tested.